Synopsys Inc. has announced a low-power design flow that will implement the Accellera Unified Power Format (UPF) version 1.0 in its IC verification and implementation products in the second half of 2007. It's similar to a recent low-power announcement by Cadence Design Systems but it's a different low-power description format.
EDA vendors have been locked in a bitter dispute between the Common Power Format (CPF), developed by Cadence and now managed by the Silicon Integration Initiative (Si2), and UPF, backed by Synopsys, Mentor Graphics, and Magma Design Automation. Both UPF and CPF allow users to specify power intent and constraints throughout the RTL-to-GDSII design flow.
UPF was released as an Accellera standard in late February. An IEEE low-power study group, designated IEEE P1801, grew out of the UPF effort and is seeking to converge CPF and UPF. Cadence, however, believes that convergence should take place within Si2, and the Si2's Low Power Coalition has decided against donating CPF to IEEE P1801.
Synopsys announced Thursday (March 29) that it is enhancing its Discovery verification platform, its Galaxy design platform, and its DesignWare intellectual property (IP) to support UPF 1.0. The company claims to offer a complete low-power solution today that's proven by over 20 successful multi-voltage tapeouts, spanning the entire design flow from system-level tradeoffs to a complete RTL-to-GDSII implementation and signoff.
Synopsys claims that Discovery provides power-aware simulation and equivalence checking, and static analysis of designs that use multiple power domains, level shifters, isolation cells, and retention memory. Galaxy claims to implement multi-voltage and MTCMOS power gating, clock gating, multi-threshold libraries, and dynamic and leakage power optimization.
"Synopsys' entire solution will support UPF in the second half of 2007," said Rich Goldman, vice president of strategic market development at Synopsys. "This is important since it enables designers to take advantage of Synopsys' complete and tapeout-proven low power solution, using an open industry standard approved by a majority of the EDA industry for interoperability."
In January, Cadence announced its Low Power Solution, which brings CPF compliance to most of Cadence's digital IC design and verification tools. Both CPF and UPF currently work from the register-transfer level on down, and do not address system-level design.