Will an effort to develop public domain benchmarks for CAD research lead to more energy-efficient MP3 and MPEG2 decoders? It's a possibility, according to researchers at McMaster University in Hamilton, Ontario (Canada).
Frustrated by the lack of public domain benchmarks for real-world applications, Nicola Nicolici, associate professor of electrical and computer engineering at McMaster University, joined with two graduate students to develop Verilog source files for MP3 audio and MPEG2 audio/video decoders. What started as a side project to build benchmarks for CAD research has turned into a full-time effort to improve the energy efficiency of MP3 and MPEG2 micro-architectures.
Verilog source files for both synthesis and verification are publicly available on line for anyone who wants to use them for research purposes. The decoders have been prototyped in Xilinx FPGA boards, and according to Nicolici, the MPEG2 decoder provides a complete enough solution so that one can hook up speakers and watch Seinfeld DVDs.
"There is a lack of benchmarks of decent size in the public domain that have source code available," Nicolici said. Currently available benchmarks for CAD research, he said, are outdated and very small, and industry has been unhelpful.
This lack of benchmarks became a problem when Nicolici's graduate student, Henry Ko, developed an RTL test analysis tool that inserts scan chains after analyzing area and performance penalties. "Henry's tool has to analyze all the source code and all the control and data flow graphs, and you need an understanding if the algorithms scale or not," Nicolici said. "If you have a benchmark with a few hundred flip-flops, that doesn't give you much input."
Ko then led the effort to build the MP3 decoder, which took about 5 months. It employs two blocks with less than 600 flip-flops clocked below 4 MHz, while satisfying sample rates of 48 Ksamples/second.
Graduate student Adam Kinsman took the lead on the MPEG2 audio/video decoder, which took nearly a year. It has clock domains that run at 54 MHz, 40 MHz, 25 MHz, and 12.28 MHz. It uses 3,337 flip-flops and 10,615 4-input lookup tables, with 28 2 Kbyte RAM blocks and 3 18-bit fixed-point multipliers, including Ethernet, ZBT memory, audio and SVGA controllers.
"From what we've seen, we're fairly competitive in terms of resource usage and power," Kinsman said. "This can be used not only in terms of benchmarking, but people might want to take it and experiment and push the design further and make improvements."
Nicolici is hesitant to say how the MP3 and MPEG2 decoders compare to commercial implementations, noting that his research group hasn't done a market search and that FPGA-based prototypes can't be directly compared to high-volume ASIC implementations in terms of power. "We're not competing with commercial solutions, but we feel we've lowered operating frequencies while meeting real-time constraints," he said.
Meanwhile, Nicolici said, anyone who's doing CAD research and is in need of high-level, real-world benchmarks may find the MP3 and MPEG2 decoder source code to be useful. "We need some formal benchmarks that can be available to everybody," he said.