SAN JOSE, Calif. Imagine a future cellphone with 32 Gbits of flash capable of playing high def video and ranging across networks from the oldest GSM to the latest 3G. That's just one of many future concepts enabled by chip designs that will be described at International Solid State Circuits Conference in February.
Renesas Technology will describe at ISSCC a mobile application processor that can decode 30 frames/second of H.264 video at 1080-progressive resolution while consuming just 342 milliwatts. The 65nm chip fits into a 6.4x6.5 mm package and runs at up to 500 MHz.
Panasonic will detail an even bigger step in low power media with an intermittent operating technique that reduces power consumption for audio playback to just 9.6 mW on its 45 nm application and baseband processors.
Toshiba and SanDisk engineers will describe a 32 Gbit NAND flash chip to meet the memory needs of such handsets. The 113mm2 device fits into a microSD card. It packs three bits per cell and is made in a sub-35 nm process.
In wireless chips, Qualcomm will detail a sing RF CMOS transceiver that can handle services ranging from GSM to UMTS bands 1 to 6 and 8 to 10. The transceiver can also handle global positioning system functions.
In imagers, Canon will discuss a 3.3 Mpixel CMOS sensor that uses new column readout circuits to lower noise by 30 percent. The chip promises higher quality video and imaging for mobile devices.
Finally, researchers from Elmos Semiconductor and the Helsinki University of Technology will detail a new interface to a micro-gyroscope. The design reduces the size of the interface to 2.5mm2 in a 35 nm process and cuts the sensor startup time to 0.4 seconds.