Supporting the new encoding scheme and maintaining backward compatibility to the earlier versions of the spec are the two chief implementation challenges engineers face with PCIe 3.0, Yanes said.
Indeed, one test engineer said it is requiring significantly more gates in the FPGA his company uses in a protocol analyzer. For example, just finding the start of a new byte is a more complex task, he said.
Supporting the new and old encoding schemes may force some designers into using two physical layer cores arbitrated by a switch. Products will at least have to support two phase-lock loops to handle the 8 and 5/2.5 GHz clocking.
Thus PCIe 3.0 chips are expected to require at least a 65nm process technology. "We don't envision people using 90nm," Yanes said.
It's not clear yet what levels of equalization the new spec may require. Gennum Corp. announced earlier this year it is licensing silicon controller and physical-layer blocks for PCIe 3.0 that use five-tape decision feedback equalization.
Motherboard makers will still be able to use four-layer boards for PCIe 3.0 designs. However they may need to adopt new trace routing techniques and face impedance margins tighter than today's 85 Ohm limits.
Both PCIe versions 3.0 and an updated version 2.1 support a handful of new features. They include atomic operations, TLP processing hints and ID-based ordering capabilities that will be particularly helpful for handling parallel operations in multicore systems.
Yanes said he was not aware of any more aggressive features in the works for PCIe to support emerging parallel programming constructs still in an early research phase. One source said Advanced Micro Devices and Hewlett-Packard have proposed multiplexing extensions for 3.0, but the proposal has not been released or voted on by the PCI SIG board yet.
At the conference, Synopsys Inc. announced it has released PCIe 3.0 controller, physical layer and verification blocks to early customers. Cadence and nSys Design Systems also announced verification IP for PCIe 3.0. For its part, Synthesis Research Inc. announced an integrated test bench to handle transmitter and receiver testing for the earlier 2.5 and 5 GHz versions of PCIe.