SANTA CLARA, Calif.Panelists discussing the challenges of 90-nanometer design at the DesignCon 2003 conference last week produced an interesting consensus: The way to solve the problems of 90-nm design is not to confront them head-on but to avoid them.
Pondering the litany of problems that have been observed at 90 nm including increased crosstalk, leakage currents, supply droop, design-for-yield issues and electromigration the speakers warned against trying to prevail by analysis at the end of the design. "You have to avoid these problems from the beginning of the design because you can't afford to extract them and fix them later," said Ronnie Vasishta, LSI Logic Corp.'s vice president of technology marketing.
Just how this might be accomplished was a matter of some debate. Vasishta, for his part, recommended a correct-by-design approach from the very beginning of floor planning and RTL coding. "Placement and global routing have to be comprehended during the RTL-coding process," he argued. "With all the variables that have to be considered, it's simply too complex to deal with at the gate level."
Ted Vucurevich, senior vice president and chief technology officer at Cadence Design Systems Inc., agreed. "At 90 nm the design technology has to become wire-centric, not transistor-centric," he said. "You have to look at the wiring topology and the layer assignment early on in the process."
The notion that RTL must be a description of the wiring, not simply an expression of the logic, recurred during the panel. It has also been voiced frequently by design teams (not represented on the panel) that are working with 130-nm designs.
Later in the discussion, Vucurevich returned to the theme, describing his notion of the correct front end for a 90-nm flow. "You need to begin with the construction of a functional virtual prototype," he said. "It's not possible to deal with optimization of mask-level designs at today's level of complexity. You have to deal with them at the beginning, in the virtual prototype."
He went on to describe that prototype as a view of the RTL that is placed and routed, at least at the global-routes level, based on fast algorithms that yield a conservative approximation of the final routing. The point is to find a level of abstraction at which it is possible to inspect the estimated placement and routing for obvious risks of signal-integrity or power issues, without having to do a detailed route.
It has been suggested that the pursuit of this virtual prototype will lead to code inspection tools for RTL that look not for logic errors but for structures that inherently create routing issues. Those tools would work in concert with tools that would estimate footprint, placement and major routes directly from the RTL.
Just in case such tools don't pan out, there is another alternative: platform-based design. Vucurevich described a methodology that would identify the major design blocks and pass them individually to implementation, using a combination of software on embedded processors, metal-mask programmability and some form of reprogrammable logic. Thus, much of the design work where the risks of creating signal-integrity or power problems are the highest would be done ahead of time to create the platform. The individual design would be more a matter of selecting and characterizing blocks than of designing hardware from scratch. The notion of the predesigned, configurable platform is beginning to get serious notice at 90 nm.