SAN FRANCISCO -- During the Semicon West trade show here on Tuesday, a panel of leading experts managed to reach a degree of consensus on the materials of choice for next-generation, high-k dielectrics for capacitors in DRAMs as well as gate stacks.
The panel's opinion that hafnium-based materials are in the lead to provide the high-k dielectric materials that will insulate gates from semiconductor channels was also backed up by experts attending Semicon West. The panel session also tipped that atomic layer deposition (ALD) technology is the slight favorite to become the means of laying down such thin films.
Experts also agreed that high-k for gate-stack applications could reach the production fabs at the 65-nm node. But high-k for DRAMs could come much sooner--possibly at the 90-nm node.
Not all is settled in high-k, however. At present, there are two schools of thought for high-k on the equipment side of the equation. During the event, analyst Ron Leckie of Infrastructure flashed a slide that showed how a panel of 120 experts surveyed at an ElectroChemistry Society symposium in May 2002 had split, with 50% backing ALD and 42% backing metal-organic chemical vapor deposition (MOCVD).
While ALD seems to have the slight lead over MOCVD right now, the panel generally agreed that the industry would strive to try and make one material system suit all applications as this lowered costs in development as well as in manufacturing.
"At the beginning of this year I was astounded to see the renewal of the ITRS roadmap listing 20 gate materials," said Thomas Seidel, chief technology officer with thin-film deposition vendor Genus Inc. He said equipment companies could not tolerate investigating or supporting so many different chemistries.
There are other material issues as well. Chris Werkhoven, vice president of strategic marketing at ASM International, a supplier of CVD, commented that the choices of insulator for DRAMs depended on whether stacked or trench capacitors were being supported. But he pointed out that the issues are much the same as for gate-stacks, electron mobility decay, and the possibility of using silicon-on-insulator (SOI) and strained-silicon as compensatory ways to boost mobility.
One issue is clear: DRAMs could be the driving force for high-k, according to Werkhoven. Memories with high-k could emerge quickly--possibly starting in 2003, he said.
Jeff Kowalski, president of ASML's Thermal Division, broadly agreed. "I see 90-nm as the node of insertion for high-k for DRAM and that means 2003, but gate-oxide takes more," he added, noting that high-k for transistor-gate applications would likely be introduced at 65-nm process node.
Dean Freeman, a principal analyst with market research company
Dataquest Inc., initiated more detailed discussion of the materials. The analyst pointed out that tantalum pentoxide, with a very high dielectric constant, is well known to the industry and researched thoroughly with DRAM application in mind, but is disliked as a "difficult" material.
Newer materials, however, are not so well characterized. "The gate is difficult. It may get pushed back to 45-nm node," he said.
Genus' Seidel pointed out that Samsung has published on the use of ALD to produce conformally coated deep trenches for DRAMs. He also said there is a shift to aluminum-hafnium oxide materials for DRAM and that the issues are very similar in both capacitor and gate configurations although with different contact materials the precise solutions may differ.
ASM International's Werkhoven said that for gate-stack aluminates have promise particularly those based on hafnium and possibly zirconium. He produced a slide chart aggregating leading research papers that clearly shows the domain dividing into two domains: hafnium-based solutions with the lowest leakage current in one cluster and in a second, with slightly inferior results, the very thin layers of nitrided silicon-oxide as a cluster of medium-k solutions.
Integration issues are key, said ASML's Kowalski. The physical and chemical stability of the films in the context of mass production is more important than simple measurements of dielectric constant. "Common process modules are mandatory. Whoever gets the first hafnium oxide film with good channel mobility has a great chance for dominating the market," he said.
Meanwhile, Seidel pointed out two significant recent papers that were perhaps showing the way forward. One was on hafnium silicon oxynitride: a complex high-k material with excellent mobility but leakage current only slightly lower than oxide. The second, from Samsung, was on an hafnium-aluminate material with leakage current reduced by several orders of magnitude, but with mobility reduce by half.
Away from the panel session Luc Van den Hove, vice president of silicon process technology at the Interuniversities Microelectronics Center (IMEC) in Leuven, Belgium, commented: "I think there is an industry consensus growing on hafnium-based solutions," he said.
IMEC was an early champion of atomic layer deposition having had a project in this area with ASM International for a couple of years and Van den Hove commented that the industrial partnership is now at a steady-state of activity mainly researching hafnium-based solutions.
"High-k dielectric will be used at the earliest at the 65-nm process technology node. First application is for low power. You can live with a thicker dielectric and there may be scope for the necessary interfacial layers. Also high performance applications could probably tolerate higher leakage current," he said.
So what will high performance applications use instead at the 65-nm process node? "They would have to live with medium-k dielectric such as the oxynitride materials," Van den Hove said.