MOUNTAIN VIEW, Calif. Synopsys Inc. is entering the logic built-in, self test (BIST) market this week with a tool named DFT Compiler SoCBIST, which will reduce both tester time and data volume, the company said. Synopsys joins other EDA vendors that have announced various techniques for test vector compression and expansion, and brings some new ideas to the table.
An extension of Synopsys' DFT Compiler and TetraMax automatic test pattern generation (ATPG) flows, SoCBIST will be integrated with the company's Design Compiler and Physical Compiler products, Synopsys said. It will reduce tester time more than tenfold, and data volume by a factor of 100 to 400 compared to traditional scan techniques, the company said.
The tool helps solve the problem of trading fault coverage for test time in dense system-on-chip (SoC) ICs, said David Hsu, director of marketing for Synopsys. Conventional ATPG tools provide excellent coverage of stuck-at faults and even finds ways to probe for delay or transition faults, and ATPG capabilities come in a familiar tool chain. But as logic density increases, and especially as the importance of transient faults increases, the sheer number of required test vectors grows far too rapidly, Hsu said.
"We have heard of cases where test cost has become equal to design plus fabrication cost," Hsu said. "That causes working designs to be abandoned."
The industry's earliest response to this problem came in the form of logic BIST. In this approach, a block of logic is partitioned off with test circuitry. In test mode, a pseudo-random pattern generator stimulates the block, and a signature detector examines the outputs.
Logic BIST requires only start and stop signals from a piece of automatic test equipment, so it is very conservative of data transfer time. But for pseudo-random patterns to have a high probability of good coverage requires that run-times be longer than the combined data transfer and execution times for conventional scan. The ability to extend BIST to get diagnostic information beyond the register level, or to employ it for transient faults, is still problematic.
The industry's second response has been data compression. Full scan is implemented, and ATPG creates structural patterns in the conventional manner. Then the pattern data is compressed, using either a purely lossless compression algorithm or one that compromises between compression ratio and fault coverage. The test equipment feeds the compressed patterns into the chip, where they are expanded by on-chip hardware. Results are similarly captured on the chip and compressed for shipment back to the test system.
This process preserves the structurally-derived nature of ATPG patterns, and hence minimizes run-times, while at the same time reducing data transfer times. The approach has been introduced by Mentor Graphics Corp. and by Syntest Technologies Inc., for example.
The Synopsys approach, while using different terms, fits in this category as well. Synopsys processes the ATPG patterns to extract a "seed," in effect a compressed pattern. The tool implants a hardware engine for pattern expansion at the edge of the block to be tested, and a similar compression block at the output.
Under test, the test equipment feeds the seed into the test pattern generator block, which uses it to reproduce exactly the ATPG patterns, providing a full structural test. Since the technique is essentially transparent to the ATPG software, it preserves the capabilities of TetraMax while reducing data transfer time.
Synopsys is agnostic on just how to apply the new approach. In some cases it may make more sense to apply it to individual blocks of logic within an SoC, Hsu said, and in others to take a whole-chip approach, using existing DFT tools to deal with embedded memories, mixed-signal circuitry and the like. Hsu emphasized that the compression approach did not change the tool flow or the strategy of design for SoC test, it merely reduced the problem of extended data transfers on the test system. That, in turn, gives test strategists the headroom to pursue more elusive test goals.
SoCBIST is an add-on to DFT Compiler and will be offered on a controlled availability basis with the September 2002 production release of that product. Pricing for the add-on begins at $175,000.