PRINCETON, N.J. -- Sarnoff Corp. here this week disclosed a new technology that potentially saves one day in the time it takes to fabricate semiconductor wafers by eliminating the need for a silicide-blocking process step. The technology development company estimated that the cost savings in chip-processing plants could be as much as $50 per wafer.
For 10 years, IC manufacturers have used silicide-blocking steps in wafer production to prevent devices from being damaged by electrostatic discharge (ESD) shocks through the input/output cells of circuits. High-speed silicided devices required the blocking step to keep silicide out of the shallow junctions between the circuit core and I/O pads, noted Sarnoff.
But Sarnoff said its developers have created a new design and layout technique for I/O devices to provide EDS protection without the need for blocking out silicidation. According to the company, the technology--called TakeCharge--can be easily applied to all chip foundries and it is process independent.
"This breakthrough technology will help fabs increase their profitability," said William T. Mayweather III, director of integrated circuit systems at Sarnoff. "Fabs that adopt TakeCharge will gain a substantial competitive advantage over those that continue to use the old silicide-blocking approach," he added.
Sarnoff also said the TakeCharge technology results in higher performance in ICs, including a reduction in die size. Wafer fabs using the technology will be "producing ICs that actually outperform silicide-blocked ICs in terms of speed and power consumption," Mayweather said.