Washington D.C.--March 26, 1997--Mercury Computer Systems Inc. (Chelmsford, MA) announced at the DSP World Spring Conference the company's strategy to provide an aggregate I/O bandwidth for its RACE Series of multicomputers of up to 6.4 GBps. The strategy, which includes the introduction of new system models in the second half of this year, will allow RACE systems to scale in excess of 1,000 processors of mixed types, while maintaining a single-system logical view for the developer.
Mercury's systems use a high-bandwidth system area network (SAN) interconnect architecture using a series of six-port crossbar switches. The interconnect, adopted as an ANSI/VITA standard (ANSI/VITA 5-1994), is called RACEway Interlink. Current RACE Series systems have a single RACEway Interlink port connecting each board to the SAN.
Mercury's technology strategy includes the introduction of new systems which will implement dual- and quad-port RACEway SAN interconnects. The dual-port implementation, which uses the 160-pin VMEbus, can be configured to provide an aggregate I/O bandwidth of more than 2.5 GBps and will be backward-compatible with the current RACEway Interlink standard. Mercury announced last week it will submit the specifications for the dual-port interconnect to the VME International Trade Association (VITA) Standards Organization for review and approval as an extension of the existing standard.
The quad-port systems will house several standard VMEbus slots, which will accept standard VMEbus boards as well as single- and dual-port RACEway boards, and they will contain quad-port slots designed for massive real-time processing compute engines. The number of each type of slot in a given system will depend upon the model being ordered. A single chassis can be configured with an aggregate bandwidth of up to 6.4 GBps.
Mercury Computer Systems
Fax: (508) 256-3599
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