San Jose--Aug. 25, 1997--An MIT research team described a novel computer architecture and microprocessor implementation that exploit advances in semiconductor fabrication technology to support the integration of multiple function units on a single chip.
MIT's Multi-ALU Processor (MAP) is the result of a collaboration between the Concurrent VLSI Architecture group at the MIT AI Laboratory and Cadence Design Systems Inc. (San Jose). The MAP chip's implementation was unveiled at the HOT SCHips IX Symposium at Stanford University. The MAP chip is the foundation of the MIT M-Machine experimental parallel computer.
Cadence's Design Services organization was responsible for the physical design and datapath developement of the five million-transistor MAP, an integrated device that consists of three processing clusters, a high-performance memory system, and an integrated network router. First MAP silicon will be produced on an 0.5-m CMOS process with five layers of metal by the end of the first quater of 1998.
Engineers based at Cadence's San Diego Design Center led efforts in floorplanning, power/clock distribution, and physical verification through tapeout. The Cadence team also developed and executed a new approach to datapath implementation utilizing its Smartpath technology and custom library elements. This flow facilitates cell reuse while maintaining high density, and results in greater flexiblility in optimizing size and performance. Cadence engineers were also responsible for the design of a high-performance clock distribution network which limits skew to under 500ps across the 18 mm by 18 mm chip for more than 40,000 clock loads.
The M-Machine project is an experimental supercomputer designed to overcome common bottlenecks that exist in current supercomputing architectures. It provides synchronization mechanisms, fast communication via an integrated 2-D Mesh network router, and low overhead memory protection via the "guarded pointers" implementation of capabilities.
Cadence Design Systems
San Jose, CA
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