Colorado Springs, Colo.--July 16, 1998--Enhanced Memory Systems, Inc. (Colorado Springs) announced that it is shipping JEDEC Superset enhanced synchronous dynamic random access memory (ESDRAM) engineering samples manufactured by Siemens and IBM to key customers. These samples have the lowest latency (22 ns row access, 10 ns column access, 4.3 ns clock access) and highest burst rate (166 MHz) of all SDRAM products. During sample evaluation, ESDRAM is achieving 200 MHz burst speed over the full operating temperature range. The combination of faster latency and high burst speed allow ESDRAM to deliver more than two times the sustained bandwidth of PC-100 SDRAM or Direct RDRAM in real systems.
The 16 Mbit ESDRAM architecture combines two 4 Kbit 10 ns SRAM page caches and two 8 Mbit 22 ns DRAM banks on one integrated circuit. The 10 ns cache reduces SDRAM CAS latency to 1 at clock rates of up to 83 MHz and 2 at clock rates up to 166 MHz. The fast 4.3 ns clock access time supports burst rates as high as 200 MHz. Unique early auto-precharge and bank activate features reduce pipelined page miss latency to 12 ns.
The ESDRAM setup time (1.8 ns) and clock to output delay (4.3 ns) exceed the requirements of the Intel PC-100 specification used by Intel 440BX, Via MVP-3, and Via Apollo Pro chipsets. ESDRAM is positioned to support future 133 MHz bus speed requirements in PC systems.
Enhanced Memory Systems, Inc.
Colorado Springs, CO
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