MANHASSET, NY Cadence Design Systems and IPCore Technologies jointly announced Friday (Aug. 29) that they have cooperated to develop the first digital design kit for Central Semiconductor Manufacturing Corp.'s process.
The IPCore-CSMC-Cadence 0.5-micron digital design kit is a complete RTL-to-GDS flow with all necessary steps, including logic synthesis, simulation, design implementation, RC extraction and physical verification.
Cadence claims to be the first electronic design company to integrate the silicon design chain for the two Chinese foundry CSMC in Jiangsu and IPCore in Shanghai through this RTL-to-GDSII digital design kit. The process flow uses products from the Cadence Encounter and Incisive platforms, including NC-Sim, BuildGates, Silicon Ensemble-Ultra, Assura and Dracula.
According to Cadence, the flow is well suited for CSMC's 0.5-micron technology and was designed especially for the Chinese market. "Cadence cooperates with Chinese partners such as IPCore as part of its strategy to help grow the Chinese IC design industry," said Peter Chen, president of Cadence China and Hong Kong operations. "This kit fueled by IPCore's design methodology and Cadence digital IC design and sign-off technology, along with CSMC's process kit further validates the Cadence digital flow and will help our customers shorten time-to-volume, reduce cost and ensure high quality," Chen said in a statement.
CSMC and IPCore are closely affiliated and managed by a Western-educated team headed by Peter Chen, formerly the founder and CEO of Mosel-Vitelic. Peter Chen is not related to a Cadence executive with the same name.