SANTA CRUZ, Calif. Startup FishTail Design Automation Inc. is targeting what sounds like a small niche, but the company says the potential benefits of its technology are huge. FishTail's tool, named Focus, identifies false and multicycle paths so that synthesis tools don't waste time trying to optimize them.
Despite a lack of public announcements by FishTail, Focus received some positive reviews in John Cooley's online DAC Trip Report 2003, based largely on private demonstrations offered at the Design Automation Conference last June. Cooley, moderator of the E-Mail Synopsys Users Group, called Focus "one of the best DAC 2003 tools to check out."
A production release of Focus is now available.
Simply put, Focus reads in RTL Verilog and generates optimized timing constraints. The value in the tool is its ability to pinpoint false and multi-cycle paths that don't actually need to meet timing constraints. With that information, users can drive synthesis tools, resolve problems with static timing analysis or clean up their RTL code.
"We think what we've developed is a fundamental breakthrough," said Ajay Daga, founder and chief executive officer of Fishtail. "We can provide a productivity improvement by taking a lot of time off the table. We can also allow physical synthesis to achieve better quality of results."
Daga previously served as senior R&D manager for hierarchical static timing analysis at Synopsys Inc., and was also a product line manager for Mentor Graphics Corp. Some of FishTail's technology is based on his PhD research from the University of Michigan, which showed how symbolic simulation can be used to find multicycle paths.
The eight-person start-up based in Lake Oswego, Ore., has received no venture capital funding, but has received funds from Magma Design Automation Inc., Sumitomo Corp. and private investors. The company has been quietly shipping Focus since November and is about to sign its first purchase orders, Daga said.
"We see a lot of market opportunity. We think we can deploy one seat of Focus for every three seats of [Synopsys] Design Compiler, and there are 12,000 seats of Design Compiler out there," he said. Additionally, FishTail intends to target FPGA designs, offering even greater market potential, Daga said.
With today's tools and design flows, designers don't have an easy way to identify false and multicycle paths, Daga said. Typically, they expect synthesis tools to try to meet timing requirements on every single path. When a tool can't meet timing on a given path, designers then have to figure out whether or not it's a real path used in the design.
"Customers endure long run-times in physical synthesis because the tool is trying to optimize timing where it doesn't need to," said Daga. "We've heard stories of customers spending six to 12 weeks in timing closure just dealing with false and multicycle paths."
One Focus customer is Conexant Systems Inc., which has just signed a purchase order for the tool, according to Anil Mankar, VP of Conexant's personal-computing division. "With our design team, the timing of the multi-cycle paths and the timing relationships between clocks is only in designers' heads," he said. "We have to have the person who does the static timing analysis talk to the design engineers to find these things out."
Focus, in contrast, points out the false and multi-cycle paths, thus allowing timing analysis and closure in a "more formal way," Mankar said. He estimated that the tool might save two weeks out of what is normally a four- to six-week timing-closure cycle.
Still, he noted, there are areas for improvement. At present, Focus generates a large number of paths, and Conexant would like a way to narrow that total down and tell the tool to ignore certain paths, Mankar said.
Daga said Focus is a production-ready tool that has handled some 30 designs ranging up to 5 million gates, and that it can generate false paths for 2 million gates in about an hour. "We hear from customers that it's very easy to use," he added.
The input to Focus is Verilog RTL and standard clock definitions. Daga said VHDL will be supported in future releases. The output is a constraint file in the Synopsys Design Constraint (SDC) format, as well as assertions that can be brought into a property-checking tool to prove the false and multicycle path definitions.
Daga said that several "breakthroughs" made Focus possible. One is the use of symbolic simulation to find the false and multicycle paths, as outlined in his doctoral dissertation. But two other significant elements were added at FishTail. One is the ability to automatically identify control in a design, and the other is the ability to functionally extract the design in order to simplify the Boolean logic
and "throw away" portions that don't affect control, Daga said.
Since symbolic simulation quickly bogs down with large designs, it is this functional extraction that makes Focus a practical tool. "For a large, complex design, we can take all these Boolean functions and simplify them and only worry about the small percentage that is control. That's what allows us to simulate a complex design to completion," Daga said.
Focus works in a hierarchical design flow, Daga noted. Designers can first use it to generate constraints for blocks. Then they can create "block interface models" that look at the communications between the blocks.
Focus also automatically determines different timing modes based on a clock tree analysis, and generates a constraint file for each mode, plus a common mode constraint file.
Finally, Focus produces an assertion file that captures the sensitization conditions for all false-path definitions. FishTail has verified that these assertions run with Averant Inc.'s Solidify property-checking tool.
Focus runs on Linux or Solaris platforms and costs $90,000 for a one-year subscription.
Daga explains the importance of false and multicycle paths further in an EDA Views column located at EEdesign.com.