Power integrity has become a key design factor for 130nm process technology and below. More and more chip failures are being reported industry-wide, due to I/O cell simultaneous switching output (I/O SSO). As the number of pins increase, the possibility of large supply noise on the chip and in the package due to simultaneous switching outputs increases as well.
Traditionally, the analysis of I/O SSO has been outside of the scope of EDA flows, which typically concentrated on either chip, or on package, or on PCB analysis. Global I/O SSO, however, requires a combined analysis of all these elements, and therefore requires a special methodology tailored to this purpose.
What is I/O SSO?
I/O SSO describes the noise on signal and supply lines caused by a large number of output drivers switching at the same time. As the number of output pins in the system increases, so does the probability of I/O SSO induced noise.
Compared to the core cells, output drivers consume more power, due to their need to drive large off-chip loads. The simultaneous switching of many outputs can create large current surges, resulting in the following detrimental effects on signal quality:
- Voltage collapse and ground bounce caused by the current surge can affect the signal quality of the output drivers as well as that of the drivers in the vicinity.
- The supply noise and current surge in the on-chip and the package power network can be coupled into the signal, especially when the signal lines are referenced to the supply planes in a form of microstrip or striplines.
The waveform in figure 1 shows how I/O SSO induced supply noise can be significant enough to cause timing push-out on a victim signal.
Figure 1 Timing push-out due to I/O SSO induced supply noise
As the process and I/O technologies advance, there is an increased risk of I/O SSO problems. Supply voltages typically decrease for advanced process nodes due to the need for low power and lower oxide thickness. The I/O voltage is also scaled down to ease the implementation of driver circuits. Decreasing supply voltage will increase the circuit's sensitivity to voltage changes. As a result, power integrity becomes more and more critical.
Use of high-speed I/O systems with fast signal transitions creates large current changes (di/dt) on the supply nets. This causes increased voltage drop on inductive components of both package and on-chip (Ldi/dt) supply nets. At the same time, high-speed output systems are increasingly sensitive to supply noise, which requires even smaller jitter and timing push-out caused by the supply noise.
For these reasons, the risk of I/O SSO induced chip failures increases as designs move into advanced process technologies or use high-speed I/O systems.
Trends in chip and package power delivery
The demand for increasing I/O bandwidth is driving an increase in the number of signal pins in a package. Despite efforts to keep constant the ratio of signal pins to supply pins, there is a clear indication that this ratio is actually increasing. This compounds the power integrity issues.
To reduce package inductance and provide some relief for I/O SSO noise, designers are using more expensive flip-chip packages instead of the more traditional wire-bond packages. However, such relief is quickly negated by a dramatic increase in system complexity. Therefore, even in designs using flip-chip packages, I/O SSO induced failures can be expected.
To avoid costly re-spins and project delays caused by power integrity issues, an accurate global I/O SSO analysis flow must be applied during the design phase. Once the issues are identified, the following methods can remedy I/O SSO problems:
Requirements for global I/O SSO analysis
- Improving package design
- Optimizing output buffer and input receiver
- Efficiently placing decoupling capacitors
- Optimizing on-chip supply network in I/O ring
Analysis of global I/O SSO requires the simulation of board, package, and on-chip circuitry in the same simulation deck. Therefore, an I/O SSO solution must support model formats used for the board and the package as well as on-chip circuitry.
On-chip modeling requires extraction of the drivers and the power-distribution environment that the drivers are operating in, including the RLC of supply networks as well as the intrinsic and intentional decoupling capacitance.
To correctly predict the current profile caused by a driver switching on the on-chip and package power distribution network, and the effect of the supply noise at the driver or receiver of an output signal, an I/O SSO simulator must support transistor-level driver Spice models.
The package model is a key element in I/O SSO analysis and a major contributor to rail collapse and ground bounce as well as coupling-induced signal distortion. A package model for I/O SSO analysis must have an accurate and complete frequency response of the supply network, the package signal routing, and any coupling between the two over a broad frequency range.
The traditional lumped RLC model defines the lower frequency response of the package. However, it is becoming increasingly important for Spice engines to support S-parameter based simulation, since (depending on the S-parameter waveform) a large amount of RLCK elements may be needed to achieve good approximation.
Different package model formats are possible in different stages of the design process. During the package design phase, package models are often created with lumped elements (RLCK) or transmission line arrays. Later, when the package is already available, package models are often derived from measurements or field solvers and reported as S-parameters, which accurately describe the frequency response of the circuit. The I/O SSO analysis has to be able to work with all of these formats.
Board models are typically represented with a small number of lumped elements (RLCK); however, they could also include transmission line or additional S-parameter models.
An effective global I/O SSO solution needs to provide both the accuracy and capacity to handle the full-chip RLC power/ground (P/G) extracted network (millions of elements), transistor level I/O cells(100k + transistors), supply and signal package models in S-parameter, transmission line, or RLCK format, and the board models. It has to be able to simulate all these different models concurrently, with reasonable runtime and Spice-level accuracy. A typical schematic of the circuit representation for I/O SSO analysis is shown in figure 2.
Figure 2 I/O SSO circuit
Previous generation tools and methodologies
Until recently, I/O SSO was seen mostly as a package effect, where an analysis included a package model with very simplified on-chip power distribution and driver models. Due to the capacity limitations of existing analog simulators, only a small number of I/O cells could be simulated. Unfortunately, this methodology has various shortcomings, as it limits the I/O SSO analysis to a "local" environment, and ignores the contribution from the "global" environment.
Since resources in the package are shared between all the I/Os, a local solution fails to model the entire load or activity on the supply traces. When only some of the I/Os are considered, these few models get all of the supply resources, and the noise is underestimated. The following describes some of the shortcomings of a "local" I/O SSO solution.
- The simulated current profile ignores the amount and placement of on-chip decoupling capacitors. Some of the high-frequency components' switching current will be filtered by the decoupling capacitors, which will affect the final current profile seen by the package.
- The current profile during switching does not consider the effect of supply noise at the driver circuit. For example, the supply rail collapse can change the signal transition time of the driver, and therefore the current profile created by the driver.
- Additional supply noise due to the on-chip power distribution is completely ignored.
- The signal distortion due to supply noise at the driver is ignored entirely. At best case, only the distortion due to coupling in the package is simulated.
- Input glitch detection due to supply rail collapse at receiver circuits cannot be simulated.
Package-focused I/O SSO analysis only simulates one of many detrimental effects of I/O SSO in a system. It can detect major problems in the package design, but it is unable to guarantee that the system will not suffer from I/O SSO related failures, including timing failures induced by ground bounce.
A new global I/O SSO methodology
While most power supply analysis is focused on the on-chip supply distribution, the I/O SSO effects are related to the interaction between on-chip supplies, driver circuits, package, and PCB board. The analysis of global I/O SSO effects requires a dedicated tool that supports large passive supply networks, a large number of transistor level I/O drivers, and package/board models with hundreds of ports that are modeled as an RLCK array or using S-parameters.
A global I/O SSO flow must include the following elements, as shown in figure 3.
- An RLC extraction engine for the on-chip power network and I/O driver connectivity.
- A transistor-level circuit description for the I/O drivers, receivers, and decoupling capacitors.
- An accurate package model in RLCK or S-parameter format.
- I/O switching scenarios for aggressor and victim signals.
- A Spice simulation engine that can simulate all the above components with analog simulator accuracy and acceptable run time.
Figure 3 Global I/O SSO analysis flow
Full-chip power integrity is one of the key challenges for designs in 130 nm process technologies and below. Design failures are frequently I/O related due to the enormous current surges caused by simultaneous switching outputs. Ground bounce and power drop become significant issues for multi-gigabit I/Os, pushing signal delays out past the acceptable timing window.
It is no longer adequate to rely on an on-chip or package-only power analysis flow. By using a well implemented global I/O SSO flow, possible signal integrity issues can be detected well before tape-out, preventing post-silicon chip failures and low chip yield.
A true I/O SSO flow must support Spice-accurate analysis of hundreds of I/Os switching simultaneously to ensure proper operation of the chip. The analysis must encompass not only the I/O buffer models, but also the power grid parasitics, package models, and I/O load.
Therefore, a new model for global I/O SSO sign-off requires an integrated solution that includes accurate on-chip extraction of the distributed power network, netlist generation, and Spice simulation of on-chip power network, buffer transistors, and frequency-dependent off-chip models.
Yu Liu is the Director of Simulation Products at Apache Design
Solutions. Yu has
extensive experience in the area of circuit design and simulation and
was previously employed at Anawork Systems, Avanti, and Anagram.
Margaret Schmitt is a senior applications engineer at Apache Design
Solutions. Prior to Apache, Margaret was employed by Sun Microsystems
where she worked on the Ultrasparc microprocessor families in the area
of full-custom design and signal integrity.