At 90 nanometers and below, leakage power management is essential in the ASIC design process. As voltages scale downward with the geometries, threshold voltages must also decrease to gain the performance advantages of the new technology. This reduction in threshold voltages has led to an exponential increase in leakage current in the transistors. Thinner gate oxides have led to an increase in gate leakage current, as well.
While ASIC power concerns were once primarily confined to the domain of battery-supplied applications often mobile, handheld devices that tend to demand more power-efficient circuits to maximize battery lifetime, the relationship between speed and leakage power has caused many high-speed ASIC designers to reconsider their design flows and methodologies.
In this article, we provide an overview of the leakage power challenges in designs at 90nm and below, and discuss the essentials of a leakage power management solution: the technologies, techniques, and tools needed to address leakage power in today's advanced designs.
Leakage power challenges at 90nm and below
Since the shift to CMOS in the 1980's, designers have enjoyed the benefits of a technology whose power consumption was largely defined by the level of switching activity in the circuit. In many cases, standby power was not an issue. When switching activity stopped, standby power was negligible, with the reverse-biased junctions between the drain and base of the transistors accounting for a large portion of any leakage current.
As technologies have scaled down to thinner line widths, voltages have also scaled down to reduce the strength of the electric fields created in the new circuits, as well as to reduce dynamic power. Figure 1 shows a simple view of a CMOS transistor. As gate oxide thicknesses (tox) decrease to as low as 12 angstroms in some 90nm processes, the voltages across the gate must be reduced to keep the electric fields from becoming too high for the insulating material.
For many mainstream designs, the scaling of supply voltages started with technologies under 0.5 microns, for which 5 volts (V) were reduced to 1V and lower. To gain the expected performance advantages for each new process generation, it has been necessary to reduce the transistor threshold voltages as well. Transistors designed to operate with threshold voltages of 1.25V as in a 5V technology are not useable in a 1V technology.
Figure 1 Simple view of a CMOS transistor.
Scaling of threshold voltages has been a large factor in the increasing leakage currents seen in recent CMOS technology generations. Figure 2 shows the relationship between performance and leakage power for typical 90 nm processes. Typically, sub-threshold leakage increases exponentially with every 65 milli-Volt (mV) decrease in threshold voltage. As the graph shows, going from an approximate gate delay of 25 picoseconds down to 8 picoseconds incurs over four orders of magnitude increase in leakage.
Figure 2 Relationship between performance and leakage current for 90 nm processes.
Working with technologies that have large standby currents is not a new concept. Designers who have used a bipolar junction technology like emitter-coupled logic (ECL) or another field effect transistor (FET) technology like nMOS are very familiar with the concept of currents constantly flowing in their circuits.
For designers who have spent their careers mostly designing in CMOS, the concept of large standby currents can be a rather new and startlingly disappointing realization, especially when chips arrive from the foundry with much higher power dissipation. A comprehensive leakage power management flow becomes essential to eliminate such surprises.
Essentials of leakage power management
Current process technologies are pushing designers into considering new design methods to reduce leakage power. As Figure 2 indicates, trading off speed is an effective way to reduce leakage power. To make use of this concept, it is necessary to create a library with a richer selection of cells based on speed and leakage characteristics.
To this end, foundries are now offering processes that make more than one threshold type of transistor available in nMOS and pMOS. These different transistor types are then used to create separate cells with the same functionality but with different speed and leakage characteristics.
Figure 3 shows a plot of library cells for a 90nm process based on the average leakage of the low Vth cells. The higher leakage cells are implemented using low Vth transistors and are plotted in yellow. The blue plot indicates the leakage characteristics for the corresponding high Vth based cells.
Figure 3 A plot of library cells for a 90 nm process.
It is also interesting to note the high and low leakage values indicated in the graph in Figure 3. These indicate that the input values for some cells can have a significant impact on their leakage.
The difference between the speed and leakage characteristics of the cells can be used to produce designs that are optimized for timing and power. Cells that are not on the critical path often do not need the performance of the high leakage cells and can use the slower and less leaky versions.
Since the input values to the cells can significantly impact their leakage, a state-of-the-art optimizer will do more than just swap cells based on average leakage numbers. Besides maintaining timing constraints, these tools also have to look at other design rule constraints (DRCs), such as maximum cell fan-outs and maximum transition times. Typically, the best final results are achieved when leakage power optimization is performed early in the flow.
For cases where using a mix of high and low Vth cells is still insufficient, more complex options are available to further reduce the leakage power of the design. These alternative techniques typically require the routing of additional lines.
One technique is to power down sections of the design, virtually eliminating leakage while these sections are in sleep mode. This technique requires the addition of power-gating transistors to stop the current flow to the selected section of the design. These can be pMOS transistors connected to the Vdd rail to isolate the section from Vdd, or nMOS transistors connected to the Vss rail.
Typically, the pMOS transistors are called headers and the nMOS footers. Some designers will use both headers and footers simultaneously to achieve maximum results. These power-gating transistors can be incorporated to control a set of cells, a row of cells, or an entire block of the design. Some cell architectures incorporate a header or footer transistor into each cell, creating the possibility of routing the sleep control using cell abutment.
Once it is determined that power gating is going to be used in a design, the designer must decide how the state of the power-gated section is going to be handled. There are three common approaches to power-gating:
- Throw away the old state and re-initialize on power up.
- Scan out the state and store it in memory to be scanned back in after power-up.
- Use special retention registers that store the state locally in low leakage latches that can be used to restore the old state after power-up.
The last approach is becoming more popular, based on its ability to quickly save and restore the state of a power-gated section. Some low-power synthesis solutions provide support for these retention registers, and will insert them into selected portions of the design if the designer so chooses.
It is also necessary to provide isolation support between power-gated sections and the rest of the design. Outputs from the power-gated sections, if allowed to float, will cause the driving gates to possibly drift to intermediate levels, creating large amounts of short-circuit or crow-bar currents in the gates they are driving, and defeating the intended power savings. It is therefore necessary to use isolation cells that will drive the outputs of the power-gated sections to known good values.
From a total flow perspective, it is important that these retention registers and isolation cells are supported not only by the synthesis and optimization tools, but also by tools that perform scan insertion, ATPG and verification.
Another technique to reduce leakage power is to change the potential placed on the body of the CMOS transistor. (The terminal labeled "B" in Figure 1 indicates the body.) By changing the potential on B, it is possible to dynamically vary the leakage and performance characteristics of the transistor. This can also be used to improve the yield of a design by allowing transistors that, due to process variations are out of spec, and must be brought back in line with their intended performance and power characteristics.
Leakage power is a growing concern in the overall design process. Unlike dynamic power, which can be managed by reducing switching activity, leakage power exacts its toll as long as the power is on.
At 90nm and below, leakage power accounts for a significant portion of the total power in high-performance designs, and plays havoc with standby power requirements in low-power designs.
This article has described how multi-threshold libraries, power-gating and variable body bias can be used to effectively reduce leakage power in 90 nm designs. Today's leading tool flows provide support for these technologies and help reduce leakage power in deep submicron designs.
Barry Pangrle is the Director of R&D for Synopsys Power Management solution, and is responsible for the Power Compiler and PrimePower product lines. Prior to Synopsys, he directed the Methodology & Automation group at Clearwater Networks and was an Assistant Professor in the Computer Science and Engineering Department at Pennsylvania State University.
Shekhar Kapoor is the senior marketing manager for Synopsys Galaxy Power products. Before joining Synopsys, Mr. Kapoor held field applications engineer positions at IBM Microelectronics and LSI Logic. Mr. Kapoor has more than 10 years of experience in IC design and the EDA industry.