Urgent call made for process tie-in
SAN JOSE, Calif. There is no longer time to speculate about integrating IC physical design, mask making and process engineering into a single flow. If something isn't done fast, the semiconductor industry will grind to a halt.
That was the clear message that burst through the normal background of equipment and materials discussions at the Advanced Reticle Forum here last week. Driving it home were keynoter Andrew B. Kahng, a professor at the University of California at San Diego, as well as representatives from the mask shop and design automation industries.
Dan Del Rosario, chief executive officer of mask maker Photronics Inc., announced a unilateral step, saying he was convening a Technical Advisory Group to create the necessary communication between the design and fabrication worlds.
As keynoter Kahng rammed home in his detailed talk, there soon will be no isolated design, mask-making and process-engineering silos. If these groups continue to work in isolation, he said, the result will be failed projects and a stalled industry. Indeed, Kahng described a two-way pipeline running between the silos, with design intent flowing downstream and process information flowing back upstream.
"For the health of the industry, we have to achieve some sort of integration across the design windows, lithography windows and process windows," agreed Del Rosario of Photronics (Brookfield, Conn.). Issues that directly impact the industry's pocketbook, such as mask cost, chip yield and reliability, all depend on optimizations that span the traditional ghettos, he said. Del Rosario argued that designers must be able to make decisions that optimize the entire flow for profitability, requiring data far more extensive than could be captured in a set of design rules or a process design kit.
But the nature of this communications link is still a matter of hot debate. Two EDA vendors, Cadence Design Systems Inc. and Synopsys Inc., presented their separate, contrasting views of the role the design tools industry should play. Both saw the solution in terms of new EDA products currently under development in their labs.
But fundamental questions remain unanswered, and there's no consensus on a solution. Some industry experts dismiss most of the talk as product opportunism, saying the bottom line is that design rules will become much more restrictive, perhaps taking the form of predefined layout fabrics that will be a part of the fabrication process and can only be configured, not altered, by a design team.
Others see the answer in an open database that design, mask-making and fabrication teams would share. Cadence and the Silicon Integration Initiative, not surprisingly, see this as a natural role for an extension to their OpenAccess application programming interface standard.
Still others see the problem as manageable by a simple extension of existing tools. "Yes, mask makers need some information on design intent," one observer commented. "But there is plenty of room within the extensibility of Oasis-the new standard format for conveying the physical design to the mask makers-to carry that data. The last thing we need right now is to be talking about an open database. Design teams won't share that much data outside their own organizations."
There is much less debate about the kinds of data that need sharing. UC's Kahng, in his paper, cited a number of examples. First, he observed that area fill and slotting-two techniques for controlling the area and distribution of metal on a wafer to improve the uniformity of chemical mechanical polishing-improved yield but had significant electrical effects too. He demonstrated that sharing data between process and design teams could sharply reduce the impact of these techniques on routing and on electrical parameters.
In his second example, Kahng addressed a major component of mask costs-the growing complexity of optical proximity correction (OPC) features in data sets. He showed that if the tool that inserted OPC was aware of the actual timing requirements of the nets on which it was working, the amount of OPC features inserted could be dramatically slashed, with a major impact on mask cost. Features whose exact shape did not affect timing or reliability could be allowed to deform during printing, and hence needed little or no OPC. Features critical to performance or reliability, such as gate poly or space around contacts, would receive more thorough correction.
Kahng estimated that such an approach could reduce the number of OPC figures by a factor of five. But this requires passing netlist and timing data to the mask shop.
In a third example, Kahng illustrated taking the data pipe to the limit: an analog design in which there were, in effect, no design rules. In this ideal world, analog designers would have accurate models of the data preparation, resolution enhancement and lithography processes, so that they could optimize yield-and even such downstream figures as project profit-during the optimization phase of analog design. In effect, designers would be working with models of the actual fabricated silicon structures during optimization, rather than with idealized device models.
This example spotlighted a major debate that lies just below the surface of the discussion. Traditionally, design, mask making and process engineering have depended on rule sets to isolate themselves from having to understand one another's technology. Fabs have provided design rules to mask and chip design shops. Mask shops have added their own lithography-related rules. In theory, if a chip design team complied with all the rules, its design would flow through the process without further design team intervention.
But this mechanism is breaking down. "Today, we are looking at maybe 2,000 design rules, a lot of them context-dependent," said Jim Jordan, vice president of marketing and business development at DuPont Photomask's BindKey Technologies (Sunnyvale, Calif.). "It is becoming impossible to comply with all the rules, and even if you do, it's no guarantee that the design will work."
Jordan and others believe that the industry must move from rules-based approaches toward model-based interactions. He noted that this has already begun in the case of OPC tools. Increasingly, the OPC features are inserted based on executing a model of the feature, testing it for compliance with a set of requirements and adjusting, iterating as necessary until the model predicts that the printed feature on the wafer will comply with the requirements.
Synopsys, since acquiring model-based OPC vendor Numerical Technologies Inc., has come out strongly in support of model-based thinking, and did so again at the forum.
The notion of model-based optimization must be replicated not only for subwavelength lithography, but for chemical mechanical polishing, process variation and perhaps other areas as well, some experts claim. And the models must be incorporated earlier and earlier in the chip design flow.
Today model-based OPC is done primarily at the mask shop. But wider use of phase-shift masks, with their phase conflicts, will eventually require OPC models both in cell layout and in chip-level place and route. Cell design and place and route tools will have to evolve to use the models. Before long, even physical synthesis tools may have to contain models of lithography, planarization and process variations.
EDA vendors are working in this direction. But mask-making and process-engineering experts fear the EDA industry could be going off in search of a product without an adequate grasp of the problem. The first goal, these sources said, is communication among all the parties at a level above specific vendor interests.