SAN MATEO, Calif. The semiconductor industry is being dragged kicking and screaming into an era in which jagged-edged technology disruptions and uncertainty have become the norm. Technology advancements aren't slowing down by any means, but experts say the rate at which the industry can absorb them isn't meeting earlier expectations.
At the same time, chip makers are doing all they can to bring the EDA industry into the loop, in hopes of narrowing gross differences in IC performance for a given technology node. To some, the move was a long time coming. The semiconductor industry will spotlight these and other pressing issues when it discloses its 2001 International Technology Roadmap for Semiconductors next week. The road map is the product of two years of cooperation among various interest groups in the United States, Europe, Japan, Korea and Taiwan, and involved more than 800 participants.
Though copies of the road map are still not publicly available, those familiar with its content say that many of the hot spots flagged by the ITRS two years ago are still in the revamped version. These include design sharing and reuse, testing of high-speed interfaces, integrating thin gate-oxide materials, adding new gate stack processes and fine-resolution optical-mask fabrication.
"What bothers me about the road map is that there is still a red-brick wall at 2005. It hasn't moved much from the last cycle," said Dan Hutcheson, president of VLSI Research Inc. (San Jose, Calif.).
Possibly exacerbating this problem is the fact that IC makers continue to shrink line widths faster than earlier road maps anticipated, which tends to accelerate the due date for new materials and technologies. In a draft summary report, the ITRS committee admitted that the move to 0.13-micron process technology came a year earlier than projected. This is because the 30 percent reduction in feature size that marks the shift to a smaller node is occurring every two years instead of every three, as the road maps have assumed.
This has been the trend for the last six years, yet the ITRS continues to project long-term feature size reduction at 30 percent every three years. The ITRS will reevaluate its stance next year, according to the draft report.
Even so, the industry has already adopted the two-year node cycle as the de facto rule. Dean Freeman, principal analyst at Gartner Dataquest, said shrinking feature sizes 30 percent every two years "is more or less the agreed-upon set of criteria of what needs to happen at the technology node with materials and line widths."
Yet there is evidence that the rapid node movement is creating a pileup of new materials at the front end of the manufacturing process. Copper interconnect was first introduced by IBM Corp. in 1997 at the 0.25-micron technology node, yet it is only being widely adopted this year. "We're just now getting to the point where we're in full-scale production at the 0.13-micron node," Freeman said. "Companies are going to be very reluctant to introduce new materials technology unless they have a high level of confidence that it's going to meet spec and perform better."
VLSI's Hutcheson said copper expertise today is still limited to the top integrated-device manufacturers (IDMs). "Part of the problem is that technology is pulling away from the industry's ability to implement it," Hutcheson said. "This is why IBM has become the world's largest ASIC supplier."
At the same time, the semiconductor industry is being forced to reckon with issues that in the past had fallen outside its purview. One of these is EDA, which plays a central role in the 2001 road map.
"This is the first time we've been able to put together a road map that gives strong direction to the academic and EDA community," said Gary Smith, chief EDA analyst at Gartner Dataquest. The last road map, in 1999, was too microprocessor oriented to be broadly applicable, he said, whereas the 2001 road map emphasizes the problems of system-on-chip design.
More participation from the EDA industry is sorely needed because fabless IC makers are fast falling behind the IDMs in device performance. Desktop processors from Intel Corp. are exceeding 2 GHz at 0.13 micron, while fabless IC houses are lucky if they pass 500 MHz using a foundry with the same process node, Hutcheson said.
"If you look at the stuff the fabless guys produce, they have typically half to one-quarter of the total performance of the transistors. The lag between the design and process is what's causing that gap," he said.
The road map acknowledges the cost of design as a major bottleneck, and has sent out a call for action to improve predictability in such areas as design reuse, implementation platforms and process variability. Another area that needs work is modeling of nanometer-scale phenomena such as increased leakage, single-event upset and atomic-scale effects, as well as the impact of silicon-on-insulator and mixed-signal circuits.
Moreover, IC makers are asking their EDA brethren for more models of electricals, thermal dissipation, thermomechanical stress and environmental impact. The road map calls for modeling, analysis and estimation tools for coupled interconnects, IR drop and ground bounce, thermal impact on device off-currents, mutual inductance, substrate coupling and other effects.
Ready to listen
EDA vendors appear ready to listen. "We view the ITRS as an important road map for semiconductor technology, and use it as a baseline to help guide our research in advanced EDA technology," said Don MacMillen, vice president of the advanced technology group at Synopsys Inc.
The road map also flirts with new device structures and "non-CMOS" technologies that are likely to appear after the 0.06-micron technology node. Many variations of these devices including double-gated MOSFETs and single-electron transistors will be described next month at the IEEE's International Electron Devices Meeting.
"There's an increased treatment of advanced new devices, things that are beyond planar bulk CMOS," said Bob Doering, co-chair of the U.S. ITRS working group and senior fellow at Texas Instruments Inc.
But one thing that won't likely change is a firm grounding in silicon. "You don't replace silicon, you simply add new materials to silicon," said Gerald Marcyk, director of components research at Intel.
Observers cautioned that the road map should not be seen as an irrefutable industry directive. "It's not so much a prediction of what will happen as a gauntlet on some targets we all agree are worth pursuing by the whole industry," Doering said.
But its purpose is no less diminished. The ITRS can help winnow down the most promising technologies in order to avoid wasting billions of research dollars on projects that end up getting scrapped, as was the case with X-ray lithography, analyst Hutcheson said.
And these days, IC makers have no choice but to spend wisely. "It takes half a billion dollars a year to stay within six months of the cutting edge if you're an IC maker," he said. "The days of walking into Applied Materials and plunking down a hundred million to get the tools and process are really gone."