# Measuring Sub-Picosecond Jitter in A/D Converters for Wireless Applications: Part 2

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New single-IF heterodyne receiver schemes, as well as sophisticated power amplifier linearization algorithms, are imposing challenging requirements for high-IF handling capability on analog-to-digital converter (ADC) performance. These factors, along with the perspective of integrating RF front-end and IF ADC rather than integrating the ADC itself with a digital downconverter (DDC), are pushing the converter's inherent jitter performance well below half a picosecond.

In fact, the main limitation to the resolution of each of these systems remains the ADC's signal-to-noise ratio (SNR). But the SNR of 12+ bit converters is in turn limited by jitter when the IF of the receiver is pushed any higher than 70 MHz. This leads to the need for a reliable, direct way to assess ADC jitter values.

In this two-part series, we'll detail a way to measure sub-picosecond jitter performance in an A/D design. In Part 1, we looked at ways to extract the cycle jitter, ways to remove dynamic effects and nonlinearities, as well as data capture and extraction issues. Now in Part 2, we'll further the discussion by exploring the impact of jitter on SNR plots as well as the use of the sub-picosecond measurement technique for the development of a 14-bit ADC test chip.

**Jitter Impact on the SNR Plot**

The jitter value extracted from Figure 3 in Part 1 finds full confirmation in the SNR performance tested on the experimental converter at the same sampling rate. The SNR predicted by making use of Equation 1 in Part 1 is limited to 57.1 dBFS at 65 MSamples/s, 150MHz. On top of that, the signal-to-noise limitation due to jitter almost perfectly matches the SNR behavior depicted in Figure 4 below.

The profile of SNR vs. f_{IN} collected at 65 MSamples/s is shown in Figure 4 in the plot along with the theoretical SNR limitation set by the jitter (a flipped-over logarithmic curve, as calculated from Equation 1). The best fitting value of the one-cycle jitter turns out to be t = 1.48 ps, which is right in line with the 1.51-, 1.42-, and 1.44-ps predictions just achieved via the novel technique. Since designers usually resort to the derivation of T by fitting the SNR at high input frequency, this crosscheck is probably the best accepted validation of the coherent sampling method.

**Figure 4: SNR performance vs. fIN of a preliminary silicon for a 14-b switched-capacitor pipelined ADC measured at 65 MSamples/s, -1 dBFS.**

The 73-dBFS SNR ceiling observed at low-IF input (1 MHz) is set by the 1.25LSB thermal noise shown in Figure 2 from Part 1. It can be also tested by feeding the ADC a high IF but very small amplitude input, such as 20 dBFS. The voltage noise caused by jitter is minimized since the slope is proportional to the waveform's amplitude (is calculated using Equation 2 in Part 1), hence the noise floor is constituted, to a first order, by thermal noise. When referred back to full scale, i.e. when expressed in dBFS, the SNR tested in this condition at 150 MHz is virtually identical to the one observed at 1 MHz input.

**Going Sub-Picosecond**

Up to now, we have been able to characterize and better understand the jitter. However, the final target is to minimize jitter in order to enable high-IF operation of the ADC. Jitter values of 1 ps or more are complete showstoppers when single heterodyne solutions are considered, and the ADC chip design must be targeted to a few 100 fs.

In view of the adoption of the converter in aggressive single-IF receiver architectures, a state-of-the-art sampling rms jitter was pursued during design. The analog front-end (AFE) of the circuit is built on a sample/hold stage implemented with switched capacitor flip-around architecture, as shown in Figure 5.

**Figure 5: Flip-around sample/hold stage schematic as designed in a 14-b, 65-MSample/s test ADC.**

The aperture uncertainty is determined by the stability of the clock phase that opens the sampling switches of this stage. Therefore, since such a phase is obtained from on-chip circuitry synchronized to an external source, when experimental data documenting the performance of the part are collected without optimizing the external reference source, the SNR featured by the circuit rapidly degrades at high input frequencies. The same mechanism applies to any other device based on the signal sampling principle.

Although the specs of the expensive quartz clock source adopted to feed a time reference to the ADC sound impressive in terms of close-in noise, and although they tend to be rated with different nomenclature, it does not mean that the jitter contribution of the instrument to the ADC is to be automatically neglected. It's a matter of translating the phase noise expressed in single sideband to carrier ratio (SSCR) into rms jitter T, and looking straight at the numbers.

The SSCR(ƒn), sometimes referred to as L(ƒn), is the spectral profile given by the ratio of the phase noise power found in a 1 Hz bandwidth at the offset ƒn from the carrier, against the carrier power concentrated at ƒ_{0}. Good clock sources specify -140 dBc/Hz or better for SSCR at 1 kHz offset from the carrier, for '0 of some 10MHz. In a previous work,8 the formula to relate the time-domain and frequency-domain parameters used to evaluate the phase stability (respectively period jitter and SSCR) was derived and validated. When the popular case of narrowband frequency noise affecting a sinusoidal clock reference is considered, a mathematical procedure leads to inferring the period jitter from the phase noise according to Equation 3:

Practically, the expression converts the phase noise spectrum S_{Ψ} into frequency noise spectrum S_{'0} (according to the Laplace transform rule S_{'} = jω S_{Ψ}) and filters it through the weight function W(ƒn). In the case of cycle jitter, to account for the uniform jitter accumulation during the time span 0 to T, the transform of the boxcar rectangle function h(t) = rect(0,T) is to be used, i.e. the sinc function. The integral of the noise spectral density must be extended from the reciprocal of the total observation time, ƒ1=1/T_{obs}, to the maximum frequency allowed by the spectrum analyzer, ƒ_{2}.

For ideal 1/ƒ_{n}^{2} phase noise roll-off, Equation 3 has a straightforward closed-form solution.8 However, for the case of PLL-like phase noise profiles, a closed-form solution is not available, and after the sameness of the phase spectrum S_{Ψ} and the normalized voltage spectrum SSCR is acknowledged, the formula can be translated into Equation 4:

Equation 4 can be numerically computed via common waveform analysis tools such as Matlab or LabView. This equation proved instrumental in evaluating the external test equipment phase noise contribution to the jitter σ_{T}. The job was accomplished by using a phase noise measurement system for avionics tests, operated in phase-lock mode, and fed with the clock source running at sampling rate '2.

The plot in Figure 6 represents the SSCR(ƒn) vs. offset frequency ƒn of the external source as observed at 30 MHz, or the same frequency used in Figure 3.

**Figure 6: SSCR vs. ƒn-offset frequency profile of the clock external reference run at 30 MHz, as obtained from a phase noise analyzer.**

The flicker noise-dominated region 1/ƒ_{n}^{3} is clearly visible before 10 Hz; the characteristic in-band plateau of the PLL with some inevitable spurs ensues up to 200 Hz, after which the typical 1/ƒ_{n}^{2} roll-off of the source's VCO becomes evident up to 1 kHz and beyond. A white phase noise zone at -150 dBc/Hz is then present.

The noise profile shown can be plugged into the Equation 4, where the integral spans from the inverse of the total observation time for SNR measurements (about 4 kHz for 16,000 points at 65 MSamples/s) to the maximum frequency offset sensed (40 MHz in figure). The experiment returns a cycle jitter as high as 1.36 ps. Since the X-axis of Figure 6 is logarithmic and since in the formula the 1/ƒn roll-off provided by the sinc is balanced by the 'n term in Equation 4, the contribution of the white noise floor becomes exponentially dominant at higher 'n. Then by applying a tight bandpass filter after the clock source (for example, 4 MHz bandwidth for a filter centered at 65 MHz), the white floor is significantly shortened, and by computing Equation 4 again the reduced jitter is calculated in only 25 fs.

This state-of-the-art number emphasizes both the accuracy, as well as the extreme difficulty of the measurement. This contribution is to be discounted from the aperture jitter inferred from the SNR by means of Equation 1, in order to isolate the additional aperture uncertainty introduced by the sole on-chip regeneration/distribution circuitry.

**Applying the Measurement Technique**

In the case of our test chip, once the noise of the external clock is filtered out as described above, the total jitter estimated through the technique dramatically decreases to about 450 fs, as shown by the interpolated curve in Figure 7 measured with a 150 MHz input. In fact, the RMS subtraction of 1.36 ps calculated after Figure 6 from 1.44 ps obtained from Figure 3c gives about 470 fs, in very fair agreement.

**Figure 7: Coherent sampling technique applied after tight bandpass filtering is applied to the external clock.**

Notice that, should the highest noise value of approximately 4.2 LSB observed in Figure 7 be used in the evaluation of jitter, a σ_{T} = 593 fs would be calculated, as opposed to the real figure of 455 fs. The error would translate into a pessimistic prediction of the SNR in excess of 2.3 dBFS at 150 MHz IF. This circumstance is a warning against the potential inaccuracies inherent to coherent sampling methods, in case the user tried unreliable shortcuts. The parametric nature of the method proposed allows instead to smooth out any punctual anomalies, and to provide for a very robust estimate of the aperture uncertainty.

Finally, after a careful internal decoupling of the supply rails used for the clock buffers was carried out, the best performance yet for a CMOS-based clock was observed through coherent sampling, as depicted in Figure 8.

**Figure 8: Final jitter test run on the optimized clock-decoupling chip version with external filtered clock.**

The previous test has been performed again at 150 MHz. The absolute magnitude of the shaping caused by the jitter is significantly reduced as compared to Fig. 3c, thus Figure 8 suffers more from statistical variability. Still, the prediction of σ_{T} based on the interpolated curves is as low as 250 fs. And, only at this point, the timing ambiguity associated with the on-chip clock pre-amplification and distribution circuitry is in agreement with the simulations run via standard Spice and SpectreRF techniques during the design phase.

The latter jitter figure is fully confirmed by the improvement in SNR shown in Figure 9, where the overall noise performance tested at 61.44 MSamples/s and 150 MHz increases dramatically from the 57.1 dBFS previously observed in Figure 4 (without bandpass filter) to as high as 70.7 dBFS (with bandpass filter), i.e. more than 13 dB improvement.

**Figure 9: 'IN sweep at 65 MSamples/s sampling rate on a BiCMOS 14 bit A/D test chip converter for wireless infrastructure applications.**

Moreover, the SNR keeps to an excellent 69.3 dBFS at 220 MHz. The characteristic concave profile of the SNR at high IF is the signature of the prevalence of jitter contributions on the SNR, starting at 100 MHz and beyond.

Such an optimal aperture jitter figure qualifies as the best performance reported to date for CMOS-based (i.e., non-ECL/PECL) clock circuits. As a benefit of the jitter optimization, the low-IF performance of the ADC measured in 73.2 dBFS SNR, 11.9 ENOB, -92 dBc SFDR at 65 MSamples/s and 1MHz keeps to 69.3 dBFS SNR, 10.7 ENOB, -70dBc SFDR at 220 MHz, making the design ideas experimented in the ADC uniquely suitable for aggressive single-downconversion receiver chains.

The total power consumption of the ADC is about 1 W at 65 MSamples/s, internal voltage reference, consumed out of 3.3 V analog and digital supply, and 3.3V output driver supply. The latter can be lowered to 1.8V achieving yet better SNR performance without any impact on the data capture window. When external voltage references are provided to the circuit, for example to implement a form of analog mixing or basic gain control into an acquisition system, the consumption lowers to about 900 mW. The maximum input range recommended is 2 Vp-p.

All the data presented was collected with a sinusoidal input of -1dBFS amplitude to prevent signal clipping. The chip was tested in a standard TQFP-64 package with PowerPad technology, to guarantee minimal variations of performance between -40 to +85 deg. C and across the 2.7 to 3.6 V extended analog/digital supply range.

**References**

M. Shinagawa, Y. Akazawa, and T. Wakimoto, "Jitter analysis of high-speed sampling systems", IEEE Journal of Solid-State Circuits, vol. 25, no. 1, Feb. 1990, pp. 220-224.

Y. Langard, J.-L. Balat, and J. Durand, "An improved method of ADC jitter measurement", in Proceedings of the IEEE ITC, Washington, DC, 1994, pp. 763-770. G. Chiorboli, M. Fontanili, and C. Morandi, "A new method for estimating the aperture uncertainty of A/D converters", in Proceedings of the IEEE IMTC, Ottawa, Canada, 1997, pp. 632-635. T. Kuyel, "Method and System For Measuring Jitter ", U.S. Patent 6,640,193. M. Mahoney, DSP-Based Testing of Analog and Mixed-Signal Circuits. IEEE Computer Society Press, Piscataway, NJ, 1987. A Zanchi, I. Papantonopoulos, and F. Tsay, "Measurement and Spice prediction of sub-picosecond clock jitter in A/D converters", in Proceedings of ISCAS 2003, May 2003, Bangkok (Thailand), vol. 5, pp. 557-560. A. Loloee, A. Zanchi, H. Jin, S. Shehata, and E. Bartolome, "A 12b 80MSps pipeline ADC core with 190mW consumption from 3V in 0.18¼mm digital CMOS", in Proceedings of ESSCIRC 2002, pp. 467-470, Florence (Italy), Sep. 2002. A. Zanchi, A. Bonfanti, S. Levantino, and C. Samori, "General SSCR vs. cycle-to-cycle jitter relationship with application to the phase noise in PLL", in Proceedings of the IEEE SSMSD, Austin, TX, 2001, pp. 32-37.
**About the authors**

*Alfio Zanchi is a mixed-signal design engineer working on high-speed ADCs with the Wireless Infrastructure business unit of Texas Instruments, Dallas, TX. He holds a PhD degree in Electronics and Communications Engineering from the Politecnico di Milano, Italy. Alfio can be reached at alfio.zanchi@ieee.org. *

*Ioannis Papantonopoulos is a test and systems engineer working on data converter and RF products in Texas Instruments' Wireless Infrastructure business unit, Dallas, TX. He received his BSEE and MSEE degrees from the University of Maine at Orono, and an MBA degree from Southern Methodist University, Dallas, TX. He can be reached at yiannis@ti.com. *

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