PARIS – Atrenta Inc., a provider of early design closure solutions, and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) announced they have joined forces to enhance the quality of delivered synthesizable IP using Atrenta's SpyGlass platform.
The SpyGlass solution, Atrenta said, provides an integrated platform for analysis, debug and fixing with a set of capabilities for structural, functional, clocking and electrical issues all tied to the RTL description of design.
Parameters such as syntax correctness, power consumption, clock synchronization, testability, timing constraints and physical routability are examined and optimized, the company continued. Atrenta GuideWare is a set of pre-packaged methodologies for Early Design Closure. For additional information about Atrenta's SpyGlass, click here
Atrenta and TSMC said they plan to jointly define a subset of Atrenta's GuideWare methodology for soft IP handoff and IP acceptance. Using Atrenta’s design metrics and datasheet generation capability, a series of comprehensive reports will be created automatically for each IP block and will be available to end customers. The reports will cover items such as completeness of the design intent for the IP, design profile statistics such as instance, flop and latch count and testability, timing and power information.
Note that early October TSMC expanded its IP Alliance to incorporate a soft IP program that improves soft IP readiness for advanced technology nodes and drive earlier time-to-market.
The new program aims to enrich TSMC’s IP alliance portfolio, to encourage soft IP innovation and reuse through TSMC’s Open Innovation Platform initiative, and to help deliver power, performance and area optimization that is a key consideration to the success of products at advanced technology nodes.