SAN FRANCISCO—Rambus Inc. Wednesday (June 15) described the development of a fast power-on, low-power clocking technology that the company said is capable of enabling a whole new class of memory devices.
The technology, described at the VLSI Circuit Symposium in Kyoto, Japan, is capable of transitioning from a zero-power idle state to a 5+ Gb/s data transfer rate in approximately 5 nanoseconds (ns) while achieving active power of only 2.4mW/Gb/s, according to Rambus (Los Altos, Calif.).
The new approach, developed by Rambus Labs, uses a calibrated feed-forward architecture to achieve extremely fast turn-on and turn-off, simplifying the system design and significantly reducing the overall system power requirements, according to Rambus.
The technology is implemented in a 40-nm low-power CMOS process, according to Rambus.
“Through this work, we’ve dramatically reduced system complexity and have saved substantial power while increasing performance to more than 5Gb/s per differential link,” said Jared Zerbe, technical director at Rambus. “When incorporated into an SoC-to-memory interface, or SoC-to-SoC link, this development can significantly reduce the memory system power and time-to-first access, driving us closer to the vision of energy proportional computing.”
Zerbe said Rambus Labs would continue to develop the technology, pushing speed and performance. Asked when the technology might be available for commercialization, Zerbe described it as still in the pure research phase.