SAN FRANCISCO—Intel Corp. will raise the curtain Tuesday (Sept. 13) on its annual developer event here, which is expected to feature a more detailed look at its forthcoming 22-nm devices featuring tri-gate 3-D transistor technology and further description of Ultrabooks, Intel's early-stage concept of a category of slim, low power laptops.
The evolution of cloud-based services, the acceleration of the roadmap for Intel's Atom SoC and the detailing by one of Intel's chief technology officer of the latest advances in research around multi-core and many-core technologies are also expected to be highlights of IDF 2011, which runs through Thursday.
In May, Intel initially described its 22-nm process technology, with a surprise twist—the long awaited 3-D transistor design, dubbed tri-gate, that Intel has been developing since at least 2002. This week, Intel is expected to provide more detail about its first 22-nm chips, based on the Ivy Bridge architecture, expected to be in high-volume production by the end of the year.
According to Steven Smith, a vice president and director of netbook and tablet development and enabling at Intel, the firm will provide more technical details on the 22-nm the microarchitecture and process technology, as well as further discussion of the end-consumer benefits of the technology, which promises the potential to reduce power consumption by more than 50 percent compared to Intel's 32-nm processors. Intel will also talk about what it sees as its competitive advantages as an integrated device maker vis-à-vis fabless and fab-lite competitors, Smith said.
On Tuesday, Mark Bohr, an Intel senior Fellow and director of the Technology and Manufacturing Group within Intel, will give a "Technology Insight" presentation on Intel's 22-nm tri-gate transistors, with emphasis on how the technology will provide power-saving advantages for products ranging from high-performance servers to low-power smartphones,
Later Tuesday, Varghese George, Senior Principal Engineer and chief architect of the Ivy Bridge interconnect and integration team, and Thomas Piazza, an Intel senior Fellow and director of graphics architecture for the Intel Architecture Group, will delivera separate presentation on the Ivy Bridge microarchitecture. The presentation will examine some key elements of the Ivy Bridge design and detail how Intel's 22-nm process technology made them possible, according to the IDF agenda.