“We had never fully optimized for latency before, so we looked at
everything from packet processing to queuing and output on a single chip
with shared memory doing cut-through switching,” said Lenoski. “We have
a number of experts in networking, silicon and the customer
applications, and it’s the combination of that knowledge that lets us do
these things,” he said.
The near-GHz chip is one of several
40-nm designs now in shipping Cisco products. “We have a number of 28-nm
designs in the pipeline, but we are not in a lot of production at 28 nm
yet,” Lenoski said.
The company’s ASICs serve a range of systems including high-end,
processor-intensive routers and boxes that push the limits of virtual
switching or pack an outsized number of 40- and 100-Gbit/s interfaces.
it started work on 65-nm chips, Cisco has been increasingly involved in
physical layout of some of its designs, including Montecello. It’s
switch and router group has a full customer-owned tooling capability to
handle physical design.
Proponents of the OpenFlow initiative
said the trend toward centralized software-defined networks will
radically simplify the tomorrow's routers and switches. Lenoski doesn't
“There are real-time constraints and reachability
issues because switches and routers are distributed, deployed all over
the place, and they are not one-to-one connected to servers,” Lenoski
said. “So I think a lot of functions will stay in switches and routers,
but the ability to program and understand the network [centrally] will
increase over time,” he added.