This is a roundup of news or activities in the past few days that may be of interest to people.
Cadence has announced several verification projects using Verification IP (VIP) for ARM® AMBA® protocols, one of the industry's most widely used verification solutions for the AMBA protocol family. Leading customers, including CEVA, Faraday and HiSilicon have reduced their verification schedules. Cadence has worked closely with ARM to ensure its VIP solutions support ARM CoreLink™ CCI-400 Cache Coherent Interconnect and CoreLink NIC-400 Network Interconnect using the AMBA 4 protocols.
Imperas has released its models of the ARM Cortex-A15, Cortex-R4, Cortex-R4F and ARM1176 processor cores. These models are now available from Open Virtual Platforms™ (OVP™). Support from OVP includes example virtual platforms incorporating the cores, with the processor core models also supported in Imperas’ advanced software development tools.
LDRA has integrated their tool suite with IBM Rational Rhapsody providing a workflow from model-driven development to test and verification of software. IBM Rational Rhapsody is a UML-based modeling and code-generation tool. Thanks to this integration, developers can access the LDRA tool suite from within the Rhapsody platform to ensure that their generated code complies with industry standards, follows best-practice programming guidelines and is fully tested.
Proton Digital Systems has announced that Sanjay Srivastava has joined its Board of Directors as Executive Chairman. In this role, Sanjay will focus on driving strategic initiatives for Proton. Prior to this appointment, Sanjay was CEO of Denali and most recently SVP of IP at Cadence Design. While at Denali, Sanjay sold the business to Cadence for $315 million. Proton Digital Systems provides LDPC-based Flash Read Channel IP that drives increased endurance and longevity of Flash Memory.
Mentor Graphics has announced that its Mentor® Embedded Sourcery™ CodeBench product supports code generation for the Qualcomm Technologies, Inc. (QTI) Hexagon™ DSP architecture for control and signal processing. Mentor Graphics is the first vendor to provide a commercially supported GNU toolchain for the Hexagon DSP architecture, supporting a wide range of embedded applications, including microcontroller, signal processing and control applications, along with commercial services to support this product offering. Each Qualcomm Snapdragon processor contains multiple Hexagon DSPs, providing programmable resources for real-time modem and multimedia functions such as gaming, media and user interfaces.
Forte Design Systems has released a new version of its Cynthesizer™ SystemC high-level synthesis. Enhancements, including increased performance and capacity, have been made across the entire tool suite. The latest features include new modeling style support, expanded optimization and analysis capabilities, integration with third-party tools and improvements to CynWare™ intellectual property cores.
XYALIS and KALRAY say that XYALIS GTstyle has successfully addressed the advanced dummy fill challenges of KALRAY's MPPA-256 manycore processor, designed using 28nm process. With its complex process rules from both analog parts requiring dedicated dummy fill procedures and large digital areas with timing and race condition constraints, KALRAY's most advanced manycore processor was a challenging with respect to the layout finishing.
According to the latest NPD DisplaySearch, flat panel display (FPD) manufacturing equipment spending fell 69% Y/Y in 2012 to $3.8 billion—making 2012 the weakest year in history for FPD equipment makers. Despite the challenges facing the FPD industry, including slow demand growth as TV and PC markets mature, 2013 offers hope of significantly improved conditions.
eSilicon is now offering memory compilers targeting the networking and computing markets in TSMC's 28nm and 40nm technologies. eSilicon’s eFlex™ and eFlexCAM™ embedded memory products include ternary content addressable memories (TCAMs) and multi-port register files. These products increase bandwidth with parallel processing for packet forwarding and classification in internet routers as well as in other applications that require high-speed table lookup. eSilicon’s 28HPM TCAMs can provide performance of up to 1.6 billion searches per second (BSPS) under typical operating conditions and a latency of 1-2 clock cycles. TCAM performance is 800 million searches per second (MSPS) under worst operating conditions.
Jasper Design Automation has two new property synthesis Apps as part of the family of JasperGold Apps. The JasperGold® Structural Property Synthesis (SPS) App is used to detect and eliminate common functional design errors and ensure that code is clean before validation starts. JasperGold’s Behavioral Property Synthesis (BPS) App accelerates verification closure by leveraging both RTL and simulation information to find and fill coverage holes, thereby increasing functional coverage and raising the overall assertion density. Both Apps support SystemVerilog and VHDL languages for maximum flexibility.
Mentor Graphics has announced its next generation Embedded Sourcery™ CodeBench and Sourcery Analyzer products. Developers can now accelerate system debugging, including multiple Linux applications concurrently, by quickly and easily visualizing and analyzing complex software systems. When combining the Sourcery CodeBench and Sourcery Analyzer products, embedded developers get proven, customizable end-to-end development tools that include automatic performance analysis and efficient multi-process debugging to increase productivity.
Space Codesign Systems has version 2.4 of its SpaceStudio™ ESL hardware/software co-design software for SoC embedded systems development. Version 2.4 introduces support for AMP in multiprocessor-based designs in an environment that carries out automated hardware software partitioning. Now, engineers can explore their design options with modern multicore architectures such as the dual-core ARM® Cortex™-A9 processor featured in the latest Xilinx® and Altera® flagship FPGA’s.
Synopsys has announced that its next-generation Discovery™ Verification IP (VIP) for the ARM® AMBA® 4 AXI4™ protocol now offers a Performance Checker capability. This capability enables system-on-chip (SoC) verification teams to analyze and validate SoC performance using metrics established during the system architecture definition process, speeding up the debug of SoC performance bottlenecks.
Uniquify has relocated its corporate headquarters from Santa Clara to San Jose, Calif., to accommodate its rapid growth. The new corporate headquarters is located at 2030 Fortune Drive, Suite 200, San Jose, Calif. 95131. Phone: (408) 235-8810. FAX: (408) 904-7349. Email: firstname.lastname@example.org.
Cadence has announced the tapeout of a 14-nanometer test-chip featuring an ARM Cortex®-M0 processor implemented using IBM’s FinFET process technology. The successful tapeout is the result of close collaboration between the three technology leaders as they teamed to build an ecosystem to address the new challenges from design through manufacturing inherent in a 14-nanometer FinFET-based design flow.
ARM announced the new ARM® Cortex™-A50 processor series based upon the ARMv8 architecture. The series initially includes the Cortex-A53 and Cortex-A57 processors and introduces a new, energy-efficient 64-bit processing technology, as well as extending existing 32-bit processing. AEM hopes that this enables their partners to create system-on-chips that address diverse markets, from smartphones through to high-performance servers.
Synopsys has released a new version of their Synopsys Synplify Pro® and Synplify® Premier FPGA synthesis tools. The 2012.09 Synplify releases include new multiple error isolation and incremental fix capabilities. They have added support for Achronix Speedster 22i HD FPGAs and improved the flow with Xilinx Vivado.
Elliptic Technologies has partnered with Trusted Logic Mobility to create a content protection technology provided through the tight integration of tVault™ HDCP 2.1 with the Trusted Foundations™ security solution on Android tablets. The solution leverages hardware enforced security based on the ARM ® TrustZone® secure hardware architecture, trusted execution environments (TEE) and targets applications such as HD Video-on-Demand, Over-The-Top and IPTV.
Similarly, Xilinx has announced solutions that further extend the Zynq™-7000 All Programmable SoC's use within trusted systems with hardware and software technologies, including on-chip decryption, authentication, ARM TrustZone® architecture, commercial and open source hypervisors, IP cores, and development boards. Collectively, these technologies offered by Xilinx, Xilinx Alliance Program members and the ARM Connected Community® enable systems that must address secure boot, separation and isolation of independent software stacks, information assurance, and Anti-Tamper.
Digital Core Design has introduced the DT8051. They believe that this is the world’s most powerful tiny 8051 available on the market. The complete system with peripherals and the DoCD debugger use 6650 ASIC gates, while the standalone CPU utilizes less than 3k gates.
Meanwhile Cortus has released what they claim to be the world’s smallest 32-bit microcontroller IP core – the APS1. The APS1 has a 32-bit architecture with 16 general purpose registers. The gate count starts at about 6800 gates. In the TSMC 90 nm technology this can be as small as 0.03 mm2 (Dolphin SESAME-HD library).
Brian Bailey – keeping you covered
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