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Slideshow: ARM A57 core revealed

11/1/2012 00:45 AM EDT
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re: Slideshow: ARM A57 core revealed
Charlie_S   11/7/2012 10:21:36 PM
Re slide 7: - irrespective of whether the compiler can auto-parallelize the SpecInt code, if the benchmark includes stuff that probes how well the cores can access shared data, that 'stuff' needs to be optimized to the target hardware. - the slide horizontal axis is labelled 'threads', with an implication that each thread is running on a dedicated core. - the figures given for the A57 indicate that 4 cores give about 3 times the performance of a single core.. - this could be indicative of a potential issue of excessive latency in the interconnect that links cores to memory etc.. Re performance: claimed vs realized: @wsw1982, the marketing guys will always try and claim the biggest figure they think that they can get away with; but behind the scenes, the engineers BETTER have an EDA environment that allows them to run the actual benchmark code on a simulation of a complete test chip (albeit rather slowly...); so they know the reality already (within the simulation environment accuracy limits.... eg DDR response time modelling...). If they don't have this capability, some people may get some 'surprises' when they start to evaluate the real Si...

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