LONDON – Startup SuVolta Inc. has announced that its novel transistor technology, dubbed PowerShrink, operates down to 0.425-V, approximately 300-mV below conventional processes. PowerShrink is based on a deeply depleted channel (DDC) transistor manufactured in epitixially grown doped silicon on the surface of a conventional bulk CMOS wafer.
The progress is set to be discussed in a paper due to be presented at the International Electron Device Meeting presented by a researcher from Fujitsu Semiconductor Ltd.
The paper entitled: Advanced channel engineering achieving aggressive reduction of VT variation for ultra-low-power applications, is co-authored by Fujitsu and SuVolta (Los Gatos, Calif.).
The reduction in variation is important because leakage current in transistors is exponentially dependent on VT and power dissipation is dominated by the low edge of the VT distribution. The tighter the distribution the lower the VT can be set.
Fujitsu has demonstrated low voltage operation of a 576-kbit SRAM block based on SuVolta's PowerShrink implemented in a 65-nm CMOS process technology. SuVolta is pitching PowerShrink as an alternative to both FinFETs and fully depleted SOI (FDSOI) which are generally considered to be the major strands of process technology beyond 22-nm. Intel has already introduced a FinFET process technology.
SuVolta's is hoping that publicly disclosed progress by Fujitsu will help persuade process research groups that its approach is superior to FinFET in that it more easily supports multiple threshold voltages over a wider voltage range, and lower cost than FDSOI in that it does not require premium-priced SOI wafers as its starting point.