As the first reports on 65-nanometer design come in from the field, the good news is that there don't appear to be any problems at 65 nm that weren't there at 90. The bad news is that some of the problems that plagued 90 nm get much worse at the new node.
Designers who have completed 65-nm projects generally identify leakage current as the biggest problem, and they're turning to a variety of strategies to manage power, including multiple voltage thresholds and voltage "islands."
"Clearly the threshold leakage and gate leakage are getting significantly worse. New design techniques have to be adopted," said Dermot Barry, general manager for the system IC business unit at design services firm Silicon & Software Systems (S3).
Design-for-manufacturability (DFM) also becomes a bigger issue at 65 nm because process variations worsen, sources said. And signal integrity problems grow as wiring gets denser.
On the manufacturing side, resolution enhancement technology (RET) becomes more complex at 65 nm, said Peter Rickert, technology development manager at Texas Instruments Inc. And process variations have much more impact. "A plus/minus 1-nm variation is a much higher percentage at 65 nm, where we might be talking about a 40-nm gate length, vs. 50 or 60 at 90 nm," Rickert noted.
Nonetheless, most designers say the move to 65 nm is proving easier than the preceding shift, which took the industry from 130 to 90 nm. "I don't think there's a major disruption," said Sribalan Santhaman, vice president of engineering at processor developer P.A. Semi Inc. Existing problems worsen, Santhaman acknowledged, but at least there are "no brand-new problems." And apart from the adoption of nickel silicide for transistors, the 65-nm shift involves no major materials changes.
Gartner Dataquest expects 238 65-nm ASIC startups in 2006, compared with a meager 26, by its tally, in 2005. Many 65-nm tapeouts to date, however, are really test chips, as opposed to volume-production chips. Few have pushed the limits of 65-nm design in terms of gate capacity.
Synopsys Inc. has counted 20 65-nm industry tapeouts, 15 of them using Synopsys physical-design tools, said Saleem Haider, senior director of marketing for the EDA vendor's implementation group. Both IDMs and fabless providers have undertaken 65-nm projects, which have centered on consumer apps and desktop graphics, he said.
Cadence Design Systems Inc. has been involved in nine 65-nm tapeouts and has publicly announced its involvement with tapeouts at S3 and P.A. Semi. Magma Design Automation Inc. claims involvement in eight to 10 tapeouts.
"Every 65-nm project we've seen has a low-power method in it," said Eric Filseth, vice president of product marketing at Cadence. "They all have multiple-voltage-threshold leakage optimization. A lot are looking at power shutoff, and there's a lot of interest in multivoltage design. You have to actively manage power for every structure in the design now."
S3 is well-acquainted with techniques for reducing leakage. The company has thus far taped out three 65-nm designs for IDMs, none yet in volume; the project with Cadence focused on a 500-MHz, 100,000-gate consumer computing device.
The conventional approach to multi-threshold CMOS, Barry noted, is to use two libraries. Designers implement as much logic as possible using a high threshold voltage, which is slower but has less leakage. They then select transistors from the low-threshold library for critical nets where timing is the priority.
"The latest techniques use multi-threshold logic gates, so you have a high-Vt header or footer built into the logic gate that turns it off during idle mode. This dramatically reduces leakage," said Barry. "But the libraries are only beginning to emerge." At 65 nm, S3 also makes use of retention flip-flops, which retain their state when the circuit is powered down.
Barry called the low-power processes offered at 90 and 65 nm "a bit of a misnomer" because they may lower leakage at the expense of higher dynamic power consumption. A high-performance process will lower dynamic power, but leakage may be an order of magnitude higher. It's thus crucial to understand which power spec is more important for the given application.
For 65 nm, Barry said, S3 divides the chip into voltage supply islands that need to talk to one another during normal operation. "You need to level shift the digital signals between one supply domain and another, which can introduce timing issues," he said. "You need level shifters, and you need isolation cells from IP [intellectual property] providers."
Multiple supply domains complicate timing analysis, Barry noted, requiring more corner analysis than in the past.
In the absence of statistical timing analysis, he said, "we just take a very conservative approach."
DFM techniques introduced at 90 nm, such as via doubling, wire spreading and metal fill, are still needed at 65 nm, Barry said. "The layout of your standard cells could be affected by the location of the poly, and bends in the poly can affect timing characteristics of the standard cell. EDA tool [vendors] are responding to these challenges, but at a slow rate."
P.A. Semi taped out a 65-nm test chip in March and is aiming for a second-quarter tapeout of the full product, said Santhaman. The test chip contains a "miniature version" of the company's 2-GHz PWRficient processor CPU, along with caches and phase-locked loops.
Leakage is a "big negative" at 65 nm, so P.A. Semi created multiple voltage islands on the chip, Santhaman said. That raises challenges, such as how to verify transitions in and out of sleep modes.
P.A. Semi also uses multiple voltage thresholds, "but you've got to be careful," Santhaman said. "If voltage islands operate at a low Vdd, stay away from higher Vt cells because they won't scale well." Voltage islands also complicate signal integrity, he said, because distributing power with reasonably low inductance becomes a problem.
"Because we are operating the chip with different Vdd islands and voltages, what operating point do we pick to run our timing analysis on?" Santhaman asked. Traditional static timing analysis tools are based on single corners. What's needed, he said, are tools that address a range of voltage, temperature and process variations.
For this reason, Santhaman views statistical timing analysis as "almost mandatory" to produce reasonable yields at 65 nm. He said P.A. Semi is developing its own capability because EDA vendors aren't yet providing it.
The more companies control the process, the more it is possible to control problems such as leakage. Infineon Technologies AG recently taped out an IP macro containing an ARM9 CPU core at 65 nm as part of a 65-nm process development collaboration involving Chartered Semiconductor Manufacturing, IBM and Samsung.
"If you increase the channel length, you have a slower device but with better leakage," said Heinz Schuetzeneder, project leader for 65-nm platform technology at Infineon. "A thin gate oxide will be fast with high leakage, and a thick oxide will be slower with better leakage." Infineon also employs multiple voltage thresholds and uses multiple voltage domains, he noted.
Designers need to be aware of process variation windows, Schuetzeneder said, and for that they need optimized libraries with yield parameters from foundry partners. "Statistical timing is part of our development concept because if you make all the corners and all the variations, you end up with an exponentially increasing development effort," he added. "We're looking to the EDA vendors. It does not make sense to have refinements five years from now-we need them now."
Texas Instruments claims to have minimized leakage problems at 65 nm with its SmartReflex technologies, a combination of adaptive devices, circuit design and software for solving power and performance management problems. TI taped out its first 65-nm product in January 2005, Rickert said, and it's now getting close to volume production with that chip, a baseband product for cell phones. "We chopped the device into multiple power domains and implemented more aggressive power management on the SRAM compilers," he said. "We also have retention flip-flops-new elements in the standard library that only exist at 65 nm."
Power distribution and IR drop are also more of a concern, because with chips running at 1.2 or 1 volt, "there is just not much headroom left," Rickert said. On a 1-GHz core, even a 1-nm variation in gate length can dampen performance.
On the process side, Rickert said, 65 nm doesn't require any changes in materials, lithography or tools, except for a new post-RET design inspection tool that TI has purchased. And thus far, it looks like the yields will ramp up more quickly than they did for 90 nm, he said.
FPGA designers see 65 nm as the route to higher capacities, and they're pushing the limits of 65 nm in terms of transistor count. But they also use a regular fabric, with identical elements that are replicated many times, so the physical-design challenges are easier for them than for their counterparts in standard-cell design.
Still, some headaches are universal. "The first thing I'd say about 65 nm is that power management is extremely difficult," said Brad Howe, vice president of IC design at Altera Corp. "The second is that signal integrity is an increasing concern."
"We've had capacity issues with every tool," said Guy Dupenloup, director of design tools and methodologies at Altera. "One difficult area is voltage drop analysis; there's a lot of data to analyze there."
Xilinx Inc. can't afford to have leakage power increase at 65 nm, so it's using thicker gate oxides and multiple voltage thresholds, said Vincent Tong, vice president of product technology. Another concern, he said, is that process variations, both among wafers and within the die, are "huge" compared with those at 130 or 90 nm. "Number one, the process has to hit the window, and we work very hard with UMC [United Microelectronics Corp.] and Toshiba on that," Tong said. "The next thing is that our design has to work within this process window. We have to deploy multiple simulations for process variations."
Any advice for those contemplating the move to 65 nm? "Use an FPGA," said Altera's Howe. "We pre-solve these problems for the customer."
For those who still want to do ASIC or ASSP designs at 65 nm, Howe had this advice: "Be prepared to invest in the infrastructure you need. You can't outsource this kind of thing. You can't buy a tool and make it go away. You really need to spend the money and have the infrastructure."