In April 2006 Achronix Semiconductor Corp announced a prototype field programmable gate array that it claimed could operate at 1.93-GHz. Achronix also claimed it was the world’s fastest CMOS FPGA. Peter Clarke asked John Lofton Holt, chairman and chief executive officer of Achronix, about the chip and about his company.
EE Times: Why are you only the fastest CMOS FPGA? Is there something faster in bipolar?
John Lofton Holt: We are aware of designs in silicon-germanium that may have been faster but at an order of magnitude more power consumption and which therefore were not practical. But when you make claims about the fastest anything you have to be careful.
EE Times: What is the architecture of the Achronix FPGA?
John Lofton Holt: It’s an x and y plot with look-up tables configured in SRAM. We do have multipliers and we do have RAM but we look very much like your mother’s FPGA.
The fundamental hypothesis of the company is that nobody needs to know that internally the architecture is asynchronous and that means in terms of EDA, in terms of design, and at the foundry. In many ways making the software appear synchronous has been a bigger challenge than the hardware.
EE Times: How can you measure performance in megahertz or gigahertz if you are clockless?
John Lofton Holt: Well, it is the equivalent rate at which we process data through the architecture. So a clocked FPGA with a circuit laid out in the same way as on an Achronix prototype would have to operate at 1.93-GHz to get the same processing done in the same time that the Achronix prototype FPGA does it.
EE Times: If the architecture is similar to those of existing FPGAs what is to stop an established player suing you? Surely they’ve got these architectures covered with patents?
John Lofton Holt: We wouldn’t be doing what we are doing if we didn’t think we had the protection necessary. And because we are implementing our architecture in an asynchronous way it makes it a lot easier for us.
EE Times: Where have you had your prototypes made?
John Lofton Holt: The first, at 0.18-micron, was done on an MPW-run (multiproject wafer) through the MOSIS IC fabrication service, although in fact it was a TSMC run. The most recent devices came from a 90-nm MPW run organized by Circuits Multi Projets of France. All 22 packaged die worked first time.
EE Times: Circuits Multi Projets offers the 90-nm CMOS process from STMicroelectronics. But will you go to a pure-play foundry for your next devices?
John Lofton Holt: Yes, Chartered Semiconductor.
EE Times: You’ve announced some extreme temperature and voltage range testing on your prototype devices. That does highlight that asynchronous performance varies with these parameters. How should we derate your devices?
John Lofton Holt: We got 1.93-GHz equivalent performance at 21 degrees Celsius and 1.2-volts Vdd. At minus 196 degrees Celsius we got 2.3-GHz performance at 1.2-V. Performance does taper off with increased temperature. At 130 degrees Celsius we got 1.4-GHz at 1.0-V. But even more important for us is voltage scaling.
As you linearly decrease the voltage you get a cubic improvement in power consumption. So at 0.6-V we got 400-MHz performance on our prototype but with an 87 percent reduction in power consumption.