SPICE has been the mainstay tool for analog and RF designers for over 25 years. During that time, analog- and RF-circuit complexity has grown by several orders of magnitude while circuit geometries have shrunk by the same, yet SPICE simulators have realized only incremental improvements. The result is multi-hour, multi-day, and even multi-week runtimes even for pre-layout simulation of complex blocks such as PLLs, sigma-delta ADCs, PHYs, and Tx/Rx chains.
Design teams go through great pains with analog/mixed-signal (AMS) and digital fastSPICE simulators to thwart SPICE performance and capacity limitations. Doing so costs them more than precious time; it sacrifices the very accuracy they need in order to have confidence in their own verification results. Moreover, without SPICE accuracy, circuit-characterization factors, including parasitic simulation, verifying packaging and transmission line effects, variation analysis (corners and Monte Carlo, noise analysis, and periodic analysis), are simply meaningless.
The problem is exacerbated at the full-circuit level. With top-level analog/RF circuits reaching more than 100,000 transistors and more than 1 million total elements, design teams long ago gave up on even achieving the most basic top-level verification of DC operating point analysis for transceivers, memories, SerDes, RFICs, and similar. SPICE tools cannot converge on such large circuits, and no other class of tool can generate a DC operating point. In fact, traditional tools can run only basic "functional verification" yielding results that may only be qualitatively correct.
By breaking down the barriers to circuit simulation accuracy, performance, and capacity, new analog fastSPICE tools are fundamentally changing the way analog/RF design teams work. Dozens of companies, from top-tier semiconductor suppliers to leading-edge startups, have proven these tools on many hundreds of production designs. Using them, design teams are able to thoroughly characterize complex blocks, completing top-level DC operating-point analysis, and running targeted, full-accuracy performance simulations. With accuracy at or below the traditional SPICE noise floor, 5x-10x higher performance, and 5x-10x higher effective capacity, they produce results that would otherwise be impractical or impossible to obtain prior to tapeout.
This article describes the classes of circuit simulators, their characteristics, and their applicability to big analog/RF verification.
Classifying Circuit Simulators
Exaggerated marketing claims make it difficult to discern the real difference between circuit simulators. EDA companies commonly claim "full SPICE accuracy" for simulators that cannot produce identical waveforms as SPICE and "5x-10x performance" when this is possible only on certain circuits and even then with extensive simulator tuning. Extensive benchmarking against all leading transistor-level simulators clearly distinguishes three classes of simulators:
1) Traditional SPICE simulators that maintain true SPICE accuracy with limited performance and capacity.
2) Digital fastSPICE simulators that compromise accuracy for increased performance and capacity.
3) Analog fastSPICE simulators that produce true SPICE accurate waveforms to the SPICE noise floor 5x-10x faster, with 5x-10x higher capacity.
Based on results from hundreds of benchmarks on production circuits, Figure 1 clearly illustrates the distinctions between the three categories of simulators based on accuracy, speed, and effective capacity.
Figure 1. Circuit-simulator category comparison
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Traditional SPICE tools use the following techniques to ensure "true SPICE accuracy":
- Create a flat netlist
- Find and maintain a true DC operating point
- Utilize global tolerance settings only (most notably reltol)
- Utilize the original device equations (make no device approximations)
- Solve the full original matrix at each iteration of each time-step
Traditional SPICE tools work well for simple blocks, e.g., those with <10K elements and <1 hour transient runtimes. However, their performance and capacity are inadequate for thoroughly characterizing complex blocks and they fail to converge for many full-circuit analog/RF circuits.
Digital fastSPICE circuit simulators sacrifice some accuracy in order to provide increased performance and capacity relative to traditional SPICE. Some of the techniques they use:
- Do not generate or maintain a DC operating point
- Utilize simplified device models
- Partition into sub-circuits and independently solving the matrix for each
- Use event-driven simulation
- Require block-level simulator tuning
- Utilize hierarchy to represent "redundant" circuitry
It is not possible to use any of the above techniques without compromising some degree of accuracy, which is why traditional SPICE simulators do not use these techniques even though they have been available for over a decade. As the name "digital fastSPICE" implies, these simulators are well suited for digital designs (e.g., digital logic, memories, and SoCs) which require potentially much more performance and/or capacity than traditional SPICE, and for which inaccuracy from several percent to 10% is sufficient.
Digital fastSPICE simulators are a fundamental mismatch for analog and RF circuits, because virtually any simulation inaccuracy for analog/RF circuits can lead to a qualitatively (i.e., functionally) different results. This is unacceptable when designers require results that are quantitatively accurate to the millivolt or milliamp range (∼0.1%).
New, analog fastSPICE simulators produce true SPICE accuracy which is 5x-10x faster and with 5x-10x higher capacity, where this "true SPICE accuracy" is defined as identical waveforms at "golden" traditional SPICE simulators to (or below) the SPICE noise floor. Analog fastSPICE performance and effective capacity advantages are compared to any simulator that also produces true SPICE accuracy.
Analog fastSPICE simulators use all of the traditional SPICE techniques cited above to deliver true SPICE accuracy. In fact, these simulators often provide provably better accuracy than traditional SPICE, which is needed to deliver accurate analysis beyond transient simulation, e.g. noise analysis and periodic analysis. The exceptional performance and capacity are the result of the new clean, modular simulator architectures which enable independent optimization of every major function within the simulator, based on the latest applied mathematics and numerical analysis techniques.
With this background, it is useful to look at the advantages that analog fastSPICE tools provide on real big analog/RF verification problems.
Big Analog/RF Verification
Designers tackle two distinct types of big analog/RF verification problems: complex-block characterization and full-circuit performance simulation.
Common complex blocks in today's designs include ADCs (sigma-delta and pipelined), PLLs (fractional-N and integer-N), DLLs, DC:DC converters, PHYs, CDRs, frequency synthesizers, transmit chains, and receive chains. Complex blocks are often very sensitive and highly nonlinear. Even minor simulation inaccuracies can lead to results that are not just quantitatively incorrect, but actually qualitatively incorrect, i.e., functionally wrong. In fact, it is often desirable, and sometimes even necessary, to run complex blocks with tighter than the default SPICE tolerances in order to push down the noise floor.
Complex blocks have performance-critical emergent properties. Hence, one should characterize them as a whole, just as thoroughly as one would characterize performance-critical simple blocks. Characterization includes some or all of the following:
1. Pre-layout transient simulation
2. Post-layout transient simulation
3. Variation analysis (corners analysis or Monte Carlo)
4. Noise analysis
5. Periodic analysis (RF circuits)
Full-Circuit Performance Simulation
"Full-circuit," in the context of analog/RF verification, means the top-level analog/RF circuitry and any nominal, integrated transistor-level digital logic. This includes wireless transceivers, wireline transceivers, digital TV tuners, SerDes, high-speed I/Os (e.g., PCI, SATA, etc.) power converters, data converters, RFICs, and top-level analog/RF portions of SoCs.
Most analog/RF design teams learned, long ago, that full-circuit performance simulation is impossible, or at least completely infeasible, within a reasonable timeframe. With today's top-level analog/RF circuits often surpassing one million total elements including >250K transistors, the days when traditional SPICE could perform meaningful analysis are long past. This leaves circuit designers with the dilemma of using tools that do not have SPICE-accurate resolution, such as digital fastSPICE and/or mixed-mode simulation (e.g., AMS simulators), to verify the final transistor-level implementation.
Consider full-circuits with ADCs. With digital fastSPICE, getting to within even a few percent inaccuracy is at best very difficult. Yet at 1% inaccuracy, it is possible to verify only the ADC's most significant six bits. That is hardly sufficient for today's ADCs, which are routinely 12 bits or more. The remaining bit connections are literally unverifiable with using digital fastSPICE.
The only way the design team will know about any lower-order bit disconnects or misconnects is when the silicon does not meet specifications. A true SPICE-accurate simulator would catch such problems with DC operating-point analysis many weeks and hundreds-of-thousands of dollars sooner.
Full-circuit performance simulation tasks include:
1. DC operating point analysis
2. Functional verification
3. Package & transmission-line analysis
4. Targeted performance simulation
To illustrate the dramatic advantages which analog fastSPICE provides for big analog/RF verification, the following sections provides detailed comparative results for a wide range of pre-layout and post-layout complex blocks. The results are equally, if not more, impressive across the remaining big/analog verification tasks.
Pre-Layout Simulation Comparisons
Pre-layout simulation of complex blocks is the easiest big analog/RF verification task, yet designers struggle to complete enough pre-layout simulation with their current tools.
Table 1 shows a number of examples with traditional SPICE runtimes versus new analog fastSPICE circuit simulation runtimes.
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All comparisons are with one of the industry's two leading "golden" SPICE simulators. All examples utilize the original netlist and the designer verified the analog fastSPICE waveforms matched traditional SPICE down to the SPICE noise floor (generally 0.1% or tighter with reltol = 1E-4 or less). All performance numbers are based on equivalent hardware.
Analog fastSPICE consistently delivers at least 5x higher performance with identical or better accuracy, for circuits with >1K elements and >1 hour runtimes. The impact of doing so on these circuits is dramatic. In the first PLL example, analog fastSPICE turned three weeks into less than one day and, by doing so, turned an impractical verification task into one that is quite manageable.
Admittedly, this is a rather extreme example. The next example is a more typical PLL, where analog fastSPICE delivered 14x improvement, slashing over three days to less than 5.5 hours.
The next three examples are ADCs. AFS took the sigma-delta ADC run from over four days to about a half day, the pipelined ADC from overnight to 3.2 hours, and the video ADC from seven hours to 25 minutes.
DC/DC converters are another class of circuits which requires long transient simulations with true SPICE accuracy. Even though it is only 12.5K total elements, the multi-channel DC/DC converter did not converge in traditional SPICE. Analog fastSPICE converged and finished the required transient simulation in a little over three days. The power-IC DC/DC converter is much larger, with 33.4K transistors. Traditional SPICE did converge on this circuit, but it took nearly one week to simulate what analog fastSPICE completed in less than a day, with identical accuracy.
The remaining circuits are a receive chain, frequency synthesizer, and automatic gain control circuit (AGC) with bandgap reference and bias. Analog fastSPICE completed these pre-layout simulations 5x, 9x, and 36x faster, respectively, than the design teams' traditional SPICE simulator.
Post-Layout Simulation Comparisons
In today's complex blocks, designers disregard parasitics at their risk. Post-layout netlists generally have about 4 to 10 times more total elements than the equivalent pre-layout netlist, although the number can sometimes be much higher. Resistors and capacitors dominate the total count, but parasitics increasingly include inductance and even mutual inductance. Even though resistors and capacitors are simple components, the total element count often increases beyond 100K elements.
In many cases, traditional SPICE simply cannot converge on such circuits, and when it does converge, the runtimes can be 2x-4x or longer than the pre-layout simulation. Digital fastSPICE simulators generally do not even have sufficient accuracy for pre-layout simulation. Even designers who use digital fastSPICE for pre-layout generally consider that applying them post-layout is a waste of time, because their results will be misleading at best. This is often a moot point because of digital fastSPICE's notoriously poor support of inductors.
The first circuit in Table 2 illustrates the problems with SPICE and digital fastSPICE for post-layout complex blocks.
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It is a 3rd-order, sigma-delta ADC with ∼14x more parasitics than transistors. SPICE did not converge (DNC), so the designer tried digital fastSPICE. After block-level tuning, the designer got digital fastSPICE to complete a run in 333 hours, which is about 1.5 weeks and 18x longer than the pre-layout SPICE run.
Fortunately, in this case the designer was evaluating the simulator on a circuit that was already in silicon. The digital fastSPICE SNR was off by 5 dB. Not surprisingly, the designer deemed the accuracy unacceptable and decided not to use digital fastSPICE for such applications in the future. The designer tried analog fastSPICE on the exact same netlist and was astounded that the tool completed transient in just 29 hours with results within 1 dB of silicon.
The other examples also clearly demonstrate how analog fastSPICE easily handles otherwise impractical or impossible problems. The DLL has over 200K total elements; analog fastSPICE reduced the runtime from 1.8 days to 7.3 hours. Few design teams have 3.4 weeks to run the post-layout PLL, but most would be willing to spend the 3.2-day analog fastSPICE runtime to check it. The next example is a second sigma-delta ADC in which analog fastSPICE was 25x faster.
The last three circuits have especially high parasitic-to-transistor ratios. The video ADC is the post-layout version of the pre-layout video ADC in Table 1. There were 842K total elements and 11.3K transistors in the post-layout netlist for a ∼75x ratio. Traditional SPICE was able to converge and complete transient analysis in 8.6 days. Analog fastSPICE took only 16 hours. This 13x speedup is comparable to the 15x speedup pre-layout.
The bias circuit had a 100x ratio, did not converge in SPICE, and finished in just 48 minutes using analog fastSPICE. The last circuit, a VCO, included inductors and mutual inductors in addition to resistors and capacitors and had an overall parasitic-to-transistor ratio over 45x. The designer's "golden" SPICE simulator took 22x longer than analog fastSPICE to produce the same results.
This article has given a taste of the power which new analog fastSPICE simulators can bring to big analog/RF verification. These tools will enable design teams to do what they currently do as much as 5x-10x faster, but without any compromise in accuracy. Perhaps more importantly, they will be able to complete verification tasks that would be otherwise impractical or impossible which will turn enable them to create ever more impressive circuits.
About the author
Paul Estrada is the Chief Operating Officer at Berkeley Design Automation, Santa Clara, CA. Prior to BDA, Estrada spent nearly six years at Cadence Design Systems where he was general manager for Encounter Test, corporate vice president of strategy, and launched the Virtuoso custom design platform, Encounter digital design platform, and Incisive functional verification platform.
In 1996, he co-founded 0-In Design Automation and helped pioneer assertion-based verification as their VP verification engineering. From 1992 to 1996, Estrada was responsible for synthesis marketing at Synopsys during that business' explosive growth period. He also has experience in the semiconductor, wireless communication, and industrial automation industries. Estrada holds engineering degrees with top honors from Stanford University and the University of Illinois. He also holds three patents.