Edited by Rick DeMeis
Steady state electromagnetic compliance and susceptibility testing, such as Transverse Electromagnetic (TEM) Cell, Direct Power Injection (DPI), and Bulk Current Injection (BCI), pose a significant challenge to the analog designer. In contrast, periodic tests such as electrostatic discharge (ESD), C-R surge, impulse noise, and fast transient noise tests are not capable of evaluating signal integrity during the disturbance.
Analog outputs or traditional ESD protection elements include parasitic diode junctions to both supply and ground busses. These diode junctions rectify during an EMI event resulting in significant energy loss. Semiconductor mobility differences compound the issue when losses are not fully symmetrical in each of the rail diodes. This energy loss creates substantial offset voltages corrupting precision analog signals. External components are traditionally used to ensure that the induced noise remains common-mode between the signal pin and its respective supply buses.
Other market constraints such as assembly cost, physical form factor, and system complexity drive not only System on Chip (SoC) and multi-chip integration applications, but also limit the use of off-chip filtering and blocking components. Additionally, in sensor interface ASIC markets, the use of long harnesses to couple precision components is common. This further increases the circuit's susceptibility to external interferencean extreme example of which is found in automotive applications. The use of mature and reliable process node provides sub-ppm defectivity, high-voltage tolerance, and low die cost that automotive suppliers demand.
Single well isolation is typically avoided since it presents EMC challenges, i.e. the presence of numerous parasitic diodes and bipolar transistors. These unavoidable circuit elements preclude the ability to fully isolate devices from noise transients leading to signal loss. In addition, substrate coupling via ground referenced diode junctions is of particular concern due to the common substrate.
We have developed a novel protection structure and shown how implementing simple noise filters can increase EMI robustness.
Traditional rail diodes (diodes connected between an I/O and both supplies) when used for ESD and EOS protection in an EMI rich environment often create signal integrity issues. EMI energy will be dissipated non-uniformly in each diode, which leads to rectification of the EMI signal. Non-uniform energy loss can be caused by (but not limited to) mobility differences in the diodes, asymmetry of the coupled EMI energy, and capacitive or inductive differences in the surrounding circuitry.
EMI rectification will create substantial offsets in precision analog I/O. Because traditional rail diodes are not compatible with EMI tolerant design, a substrate-isolated bimodal SCR (silicon-controlled rectifier) was developed. The SCR was designed to manage all periodic high-energy disturbances. Once triggered, this structure provides ESD and EOS protection through a high current tolerant path to ground.
The required isolation of the parasitic substrate-Nwell diode junction is achieved via an integrated precision high resistance polysilicon resistor. This polysilicon limits current flow through the substrate-Nwell diode junction. A cross sectional diagram is shown below.
This simplified diagram of a Bi-Modal SCR protection structure shows the precision high resistance polysilicon resistor connected to pad metal.
The positive trigger voltage for this structure is determined by a Zener breakdown defined in region A of the above figure. The spacing of the N+ diffusion in the discharge bus Nwell to the pad Nwell determines this activation threshold. The negative trigger voltage for this structure is set by the avalanche breakdown of the P+ diffusion to Nwell defined in region B of the figure. The dopant concentrations of these regions determine the P+ diffusion to Nwell avalanche breakdown threshold.
Modulation of the N-channel field overlay spacing along the junction boundary can customize different threshold values. The optional polysilicon resistor between the pad metal and the N+ diffusion is positioned to limit PNP injection during rapid transients and noise on the pad metal. The SCR threshold is determined by the two floating N+ diffusion regions in conjunction with the Zener triggered P-tub current surge. These regions of higher dopant concentration focus the electric field strength near the substrate surface and the discharge bus n-well edge. Trigger voltages are selected to match the voltage tolerance of the core circuitry.