Developing ASICs requires careful design and placement of I/O cells to support the latest complex I/O standards so as to provide good signal integrity to all pins. Designers using FPGA design software can assign logic to configurable I/O cells. Modern FPGA design software packages perform a quick check to validate pin assignments and corresponding I/O standard assignments up front to ensure proper operation.
ASIC testing and fault coverage are important in the ASIC development process. ASIC testing includes boundary scan insertion, built-in-self-test (BIST), signature analysis, and automatic test pattern generation (ATPG) techniques. FPGAs already include boundary scan logic, as opposed to an ASIC design flow where designers must insert boundary scan logic and simulate it on top of the actual design logic. FPGAs have been tested extensively during manufacturing; in FPGA design flows, engineers focus on testing design functionality as opposed to device structure that already has been performed by the FPGA manufacturer.
FPGAs include advanced, low-skew clock networks for clock distribution within the device. FPGA designers must give up the freedom an ASIC designer has to implement fully custom clock networks; however, the pre-defined clock tree structure in an FPGA greatly simplifies the overall design process and satisfies most applications.
When moving from ASIC design to FPGA design, developers should take care to employ synchronous design practices. These design practices are essential for long-term, reliable operation and provide design portability for implementation in different device speed grades or device architectures. Leading-edge FPGA design software packages from FPGA vendors and third-party software vendors such as Mentor Graphics, Synplicity, and Synopsys include integrated design rule-checking and other features that enforce synchronous design practices.
Incremental design flows
Leading-edge FPGA design software packages, such as Altera's Quartus II software, support block-based incremental compilation design flows similar to the flows used for ASICs. This feature allows system designers to partition a design into several functional blocks and assign these blocks to individual team members for independent design, optimization and implementation. These blocks are then imported into a top-level system design while maintaining design performance of the blocks. Optimized blocks are reusable in subsequent projects maintaining performance levels.
Leading-edge FPGA design software packages provide innovative features for rapid system design and hardware/software trade-off analysis. A broad offering of off-the-shelf IP cores is available for using FPGAs in system design. This portfolio of IP includes embedded processors, communications functions and optimized digital signal processing functions, as well as interfaces and peripherals.
Timing closure and ECO support
Reaching timing closure is critical in both ASIC and FPGA design flows. Some FPGA design software includes automated tools and "power tools" offering ASIC-like control. Timing closure tools available to FPGA designers now includes automated physical synthesis optimizations such as automatic register duplication and register retiming to tune design performance. Manual register duplication offers FPGA designers precise control to reduce fan-out on critical paths. FPGA floorplan editors allow manual adjustment of logic placement for optimum timing.
In a typical engineering project development cycle, specification for the programmable logic portion is likely to change when engineering development begins or as all system elements are being integrated. These last-minute design changes are referred to as engineering change orders (ECOs). ECOs are small function changes in a design after it has been fully compiled (i.e., synthesis and place-and-route are completed). ECO support is a common element in ASIC design flows; FPGA design software typically now offer support for implementing ECOs on the HDL and/or netlist level depending on the FPGA vendor.
ASIC design flows are typically driven by custom scripts or make files. FPGA designers can now find the same capability in some software and tools from third-party vendors such as Mentor Graphics, Synplicity, and Synopsys. Quartus II software runs from a graphical user interface (GUI) or command-line interface. It supports a subset of the popular Synopsys design constraint (SDC) syntax used by many ASIC development tools to enter design constraints. Quartus II software also includes a new Tcl-based application programming interface (API) for scripting custom design flows.
EDA verification tool support
ASIC designers performing FPGA design for the first time will discover that many ASIC verification tools can also be used for FPGA verification. Most FPGA design software packages output netlists for EDA static timing analysis, HDL simulation, board-level timing analysis, and signal integrity analysis software. Also, formal verification tools used in typical ASIC design flows will work in FPGA flows.
There is no substitute for real-time in-system verification. FPGAs offer inherent advantages over ASICs for in-system verification. FPGA designers are empowered to make rapid iterations to test in-system using tools such as embedded logic analyzer functionality. Additionally, some FPGA design software packages can incrementally route debug signals to pins without changing HDL source files. Design fixes are also easily implemented and tested in the lab using incremental chip-editor functions to view detailed design implementation structures and make incremental modifications quickly and efficiently.
As time-to-market pressures increase, ASIC mask and development costs rise and low-cost FPGAs continue to decline in price and increase in performance and system-level features, more ASIC designers are designing with low-cost FPGAs. FPGA design software has adapted to the needs of these ASIC designers by providing a similar development environment, offering ASIC-level performance and features and offering advantages in system design and in in-system verification to further improve time-to-market benefits for FPGA designs.
ASIC-to-FPGA Design Methodology and Guidelines, Altera Corporation.
Robert Kruger is the product line marketing manager for low-cost products at Altera Corporation.
Robert joined Altera in June 1999 and is responsible for marketing Altera’s low-cost FPGA products as well as design software and tools. Prior to joining Altera, Robert was responsible for sales, marketing, and tech support for embedded systems development tools at Tribal Microsystems. He holds a BSEE from Boston University and an MBA from Santa Clara University. Robert can be contacted at firstname.lastname@example.org.