Are ASIC designs too expensive? Does FPGA performance fall short of specifications? Consider a structured or platform ASIC implementation for your next mid-performance, mid-volume chip.
Over the past year, a different type of chip implementation has been garnering a lot of attention from IC vendors and designers alike. Known as Structured ASIC or Platform ASIC (SA/PA), this design platform, a hybrid of cell-based and FPGA design technologies, targets mid-range chip volumes, in the approximate 10K-100K units per year range. SA/PA chips share a common featureblocks of silicon IP (SIP) that the designer "personalizes" with a subset of the chip's total mask set. The resultant chip sports a faster design cycle and, thus, a faster time to market (TTM), along with less expensive NRE than an ASIC. In addition, SA/PA chips exhibit higher performance and cheaper per-unit cost than an FPGA. Read on to see how SA/PA design makes sense for many applications.
The "High" of ASIC Design
No one disputes that if you need very high performance from your chip, ASIC design is a viable design alternative. However, high performance comes at a pricelong design cycles and high up-front (NRE) cost, coupled with high design risk. Typical ASIC design times at 130nm are 12 to 18 months, well beyond the 6 to 9 months needed to develop products for the heavily consumer-driven chip market. Large chip suppliers help alleviate the long ASIC development cycles by pipelining products, starting a new-generation chip prior to completion of the previous one. However, this is risky and only makes sense when a company is pretty confident of demand for very large product volumes.
Along with long development cycles, ASIC chips are expensive to develop. Figure 1 shows that a 130nm ASIC has a design cost of around $10M; of this, the mask cost is only around 10%, about $750K-$1M. At 90nm, design cost leaps to around $25M per chip. These design-cost estimates are conservative; other sources show them to be as much as double these numbers. Also in Figure 1 is the revenue per design start for the various technology nodes. The widening gap between design cost and revenue per design start points out the increase of (financial) risk as process nodes shrinkit becomes increasingly difficult to recoup the cost of an ASIC chip as process technology advances.
Figure 1: While both rise with shrinking process nodes, the increasing ASIC design risk as processes shrink results in a widening of the gap between design cost and revenue per design start
Figure 2 shows the revenues a design requires to recoup both 10x and 15x the design cost for various technology nodes. At 130nm and a desired 10x return on chip design cost, the vendor must sell around $190M of chips. If the average chip price is $25, this means the vendor must sell 7.6M chips to achieve the 10x ROI figure. Clearly, ASIC designs do not meet everyone's chip needsonly those vendors who have very high performance requirements and see a demand for a large selling volume of the chip they have developed.
Figure 2: The revenues required per chip design increase dramatically as process nodes shrink and chip development cost rises
(Source: International Business Strategies)
Over the past couple of years, FPGA vendors have turned out products, such as Xilinx's Virtex and Altera's Stratix, that come closer to ASIC speed and density. However, for a comparable design an ASIC will still win the performance battle against an FPGA manufactured at the same process node. Furthermore, FPGAs can't match ASIC power consumption and unit cost. Since FPGAs use several extra transistors per logic gate to achieve their reconfigurability, they are more power hungry than an ASIC for the same application. Furthermore, these extra devices on an FPGA result in a larger chip than what you can design in an ASIC, hence resulting in a higher cost per device. For prototyping and design feasibility studies, FPGAs make sense, as they also do for low-volume (below 10K/year) requirements. Otherwise, unless TTM is an overriding consideration, FPGA technology is limited to these uses or for applications where reconfigurability is a necessity.
Enter Structured/Platform Technologies and Products
With the decline in popularity of gate arrays, there is a gap between ASICs (along with ASSPs) and FPGAs for mid-volume applications. Several chip and EDA vendors have recognized this vacuum and have been working on hybrid ASIC/FPGA technologies and products known as Structured ASICs, Platform ASICs, or Platform SoCs. All of these designations refer to the same type of chip implementationconfigurable silicon platforms, modifiable during design, that allow one platform to address several applications. Designers configure the platforms by personalizing a subset of the mask set used to manufacture the chip. Each "flavor" of SA/PA has the following characteristics:
- Several fixed-function cell-based cores (SIP). These can be proprietary to the chip vendor or come from a third-party SIP developer.
- A fabric to customize the connectivity between and/or functionality of these cores, thus personalizing the chip for a particular application. The number of masks necessary to customize the chip can be as low as one and can go up to about ten (still only around a third of the total masks), depending on SA/PA vendor.
- Clock distribution, power grid, I/O pad-ring, memory, and other IP common to all cell-based ASICs or ASSPs.
How SA/PA vendors implement their product or technology configurability differs widely. This means that the level of design expertise and length of design time varies greatly from one SA/PA vendor to another. In addition, each vendor has its own SIP library, which also affects the effort a designer needs to complete an SA/PA design.
Table 1 lists some of the more visible structured and platform ASIC vendors. Some, such as ViASIC, ChipX, and Lightspeed Semiconductor, have non-product-specific SA/PA technology. Others, such as Fujitsu and LSI Logic offer silicon SA/PA platforms. Altera is unique in that they offer HardCopy, a technology for transferring a design from one of the company's FPGA architectures to a mask-programmable chip that is significantly smaller, less expensive, and of higher performance than the FPGA.
||Metal Programmable Cell Array (MPCA)|
||Structured Array Fabric|
||Instant Silicon Solution Platform (ISSP)|
Table 1: Representative Structured and Platform ASIC Vendors
Also coming from the FPGA side is eASIC. The company has recently announced their FlexASIC structured ASIC platforms which feature bit-stream configuring of SRAM programmed logic, like an FPGA, plus customized routing using a single via mask (Figure 3). ViASIC is another vendor offering a Structured ASIC technology you program with a single via mask. In addition, the company also has ViaPath, a design tool for optimizing, placing, and routing single-mask-programmable and other structured-ASIC chips.
Figure 3: eASIC's FlexASIC chips combine a bit-stream programmable, SRAM-based, look-up-table cell array with a single-mask-programmable interconnect fabric
Developing EDA tools and a tool flow for SA/PA use requires the tool supplier to have knowledge of the technology the SA/PA vendor is using. FPGA design tools are configured to optimize the chip design associated with a specific vendor and device-family architecture. In a similar vein, vendors of SA/PA tools have to design versions of their tools to take advantage of the architecture and IP of the configurable fabric on the SA/PA chip and how this fabric works with the embedded SIP. This is in addition to having the tools also work effectively with the ASIC-like aspects of the SA/PA design.
Enthusiastic in its support for SA/PA chips, Synplicity has customized versions of its Amplify physical-synthesis tool for both LSI Logic's RapidChip platform-ASIC and NEC's ISSP structured-ASIC technology libraries. Amplify RapidChip, for example, has custom module generators and optimizations that are specific to RapidChip (for more information, attend the LSI Logic on-demand webcast, The Platform ASIC Advantage). The tool gives users a physical-synthesis flow that lets them go from RTL code to a placed-gates handoff for backend physical implementation, thus spanning initial floorplanning through placement and full-chip timing and congestion analysis.
Other EDA vendors that have announced SA/PA products or have development efforts ongoing include Magma Design Automation with Magma SA, an RTL-to-structured ASIC synthesis tool, AccelChip, and Tera Systems. In mid-May, Magma announced the adoption of their RTL-to-GDSII chip-design flow to support floorplan creation, physical synthesis, legal placement, clock-tree synthesis, and power routing for Faraday's Metal Programmable Cell Array (MPCA) Structured ASIC devices. AccelChip touts their recently announced DSP Synthesis tool as supporting a true top-down flow for DSP algorithm development from The Mathworks' MATLAB environment to ASIC, FPGA, and Structured ASIC platforms. The company also has partnered with design-services provider Pinpoint Solutions to provide design and methodology services for DSP Synthesis customers. Working with Tera Systems, NEC has developed an ISSP-optimized RTL rule-checking and planning tool to assist in timing closure and in the chip's downstream physical implementation. LSI Logic also uses Tera Systems' TeraForm for LSI's RapidChip products.
The Benefits of SA/PA Configurability
One big advantage of SA/PA design is the application adaptability of these products. Since the designer is personalizing the chip platform for a specific use, the same SA/PA platform can target several applications in the same domain. Using a single "core" design for several products more than makes up for the cost of design flexibility, namely hits on chip size and performance compared to an ASIC chip. While developed by Elixent for an application-adaptable architecture other than a structured or platform ASIC, Figure 4 shows the cost advantage of multiple products derived from a single reconfigurable silicon platform, assuming 2M units of a $10 chip at 180nm. Similar results could be expected for a configurable architecture. You can see that even as the SA/PA's chip area increases with an increase in number of derivative products from a single chip, the ability to derive multiple products drops the per-unit cost significantly as the chip moves to smaller process nodes.
Figure 4: SA/PA application adaptability supports the development of multiple products from a single silicon platform. From a cost perspective, this more than compensates for the SA/PA area penalty compared to multiple ASIC designs for the same products
Do Structured and Platform ASICs Make Sense?
I think the answer to this question is a definite "yes." Having a type of chip that fits in-between ASICs and FPGAs offers a designer some of the benefits of both technologiesperformance and unit cost approaching that of an ASIC coupled with the reduced NRE and TTM of an FPGA. However, choosing a vendor for your structured or platform ASIC is not simple. Each vendor's technology and product has its own combination of performance, cost, and design considerations and the difference between the various SA/PA offerings is significant. As a potential user of SA/PA technology, you need to consider the following factors:
- Performance considerationsspeed, power, and application-specific specifications
- Available silicon cores (SIP)
- Ease of design
- Cost (NRE and unit)
- EDA support.
Differences in product performance between SA/PA vendors are significant. A sampling of eight of the vendors in Table 1 provided the following parameter spreads at 90nm to 180nm process nodes:
|Masks to personalize the chip:
||1 to 10|
|Maximum ASIC gates:
||1.5M to 10.5M|
|Maximum memory bits:
||1.4M to 11.57M|
|Maximum clock frequency:
||200 MHz to 500 MHz|
|Maximum number of I/O pins:
||259 to 1089|
|Power dissipation (nW/MHz/gate):
||6 to 100|
The availability of general-purpose and application-specific silicon cores is a big differentiator between SA/PA vendors. For example, in its AccelArray family Fujitsu has an Embedded CPU platform with an ARM926 CPU along with 3M gates of configurable logic and 4 Mbits of memory. Soft macros, including 10/100/1G and 10G MACs, PCIX, and USB controllers, further enhance the platform's application flexibility. More application-specific AccelArray Giga Frames use pre-diffused high-speed Giga PHY (GPHY) macros that provide a point-to-point, full-duplex, differential, serial-communications link supporting data rates from 622 Mbps to 3.125 Gbps. One of NEC's ISSP platforms has an embedded 3.125G SerDes core. The ISSP1-HS1 supports XAIU-, Infiniband-, PCI Express-, Gigabit Ethernet-, and Fibre Channel-compliant IP cores and targets networking, storage, and high-end computing applications.
LSI Logic has an extensive SIP portfolio, CoreWare, which they use for both their ASIC and RapidChip devices. Processor cores include soft and hard versions of several ARM cores, the MIPS4KE, and LSI's own ZSP DSP core. The company also offers several high-end memory interface cores and GigaBlaze, a SerDes-compliant serial communications core that supports up to 4.25 Gbps. Unique to LSI is System CoreWare, pre-designed and pre-verified subsystems comprising CoreWare SIP. Figure 5 shows an ARM926 System CoreWare subsystem, with the processor core already connected to several other SIP cores.
Figure 5: This ARM926 processor subsystem combines a RISC processor with pre-defined peripheral cores, saving the designer chip-development time and effort
There are currently some barriers to SA/PA acceptance. These include the wide variability of performance, cost, and design ease from vendor-to-vendor. In addition, there is the unproven track record of SA/PA designs which, at this time, are below 10% of ASIC designs on an annual basis (although ASIC design starts are dropping while SA/PA design starts are rising). However, several key market research firms are bullish on the success of structured and platform design.
In Looking for the Sweet Spot in Electronics Design Chain, author Richard Quinnell notes that, "Dataquest expects 200 structured ASIC design starts in 2004, growing to nearly 1,000 in 2007. IC Insights puts the 2008 sales of structured ASICs at more than 30 percent of an expected $12 billion in revenues from cell-based ASICs." Quinnell's article also indicates that iSuppli sees significant growth in structured ASIC product revenue and design starts from 2002 to 2007.
About the Author
is currently the President and Editor-in-Chief of SemiView Inc., a new company providing business, financial, and technology analysis, research, and editorial information for the rapidly growing Application-Adaptable Integrated-Circuit (AAIC) industry. His job experience includes chip-design R&D, marketing, marcom, technical editing, and on-line publishing of technical content for engineers.