As clock speeds in communications systems push into the GHz range, phase noise and jitter always key issues in analog designs are becoming increasingly critical to the performance of digital chips and boards. Timing errors in the clock or oscillator waveforms of high-speed systems can limit the maximum speed of a digital I/O interface, increase the bit error rate of a communications link, or even cap the dynamic range of an A/D converter.
Given this trend, designers of high-speed digital equipment are beginning to pay greater attention to timing issues. This paper provides digital designers with an overview of phase noise and jitter, describes their impact on system performance, and identifies common circuit techniques to minimize them.
What are phase noise and jitter?
Phase noise and jitter are different ways of quantifying the same phenomenon. In the ideal world, the duration of a perfectly pulsed signal at a certain frequency level 1 MHz, for instance would be exactly 1 microseconds, with an alternating edge every 500 ns.
Such a signal, unfortunately, does not exist. As shown in Figure 1, there are bound to be variations in the length of the period, which causes uncertainty about when the next edge of the signal will occur. This uncertainty is phase noise or jitter.
Figure 1 -- Waveform timing variations
Jitter: the time domain
Jitter is a measurement of the variations in the time domain, and essentially describes how far the signal period has wandered from its ideal value. Typically, deviations below 10 MHz are not classified as jitter, but as wander or drift.
There are two main types of jitter: deterministic and random. Deterministic jitter is created by identifiable interference signals. It is always bounded in amplitude, has specific (not random) causes, and cannot be analyzed statistically. There are four main sources of deterministic jitter:
- Crosstalk between adjacent signal traces This occurs when incremental inductance from one conductor converts induced magnetic field from an adjacent signal line into induced current. The induced current increases or decreases the voltage, thus causing jitter.
- EMI radiation on a sensitive signal path EMI sources include power supplies, AC power lines, and RF-signal sources. Like crosstalk, a noise current is induced on the timing signal path, thereby modulating the voltage level of the timing signal.
- Noise from power layers of a multi-layer substrate This noise can change threshold voltages in logic gates, or change the ground reference at the threshold voltage, which changes the voltage required to switch the gate.
- Simultaneous switching of multiple gates to the same logic state This can induce current spikes on power and ground planes, creating another opportunity for shifting threshold voltage levels.
Random jitter describes timing variations caused by less predictable influences. Temperature, which affects the mobility of semiconductor crystal material, can cause random variations in carrier flow. Semiconductor process variations, such as non-uniform doping density, can also cause jitter.
Random jitter, by its very nature, can be characterized using Gaussian distribution statistics. For example, 100 successive measurements of the period of a clock oscillator that contains only random jitter elements would appear as a Gaussian (or normal) distribution. Plus or minus one standard deviation would contain 68.26% of all period measurement data points:
- +/- 2 sigma would contain 95.4 % of all measurements taken;
- +/- 3 sigma would contain 99.73%; and
- +/- 4 sigma would contain 99.99366%.
This normal distribution yields two common jitter specifications:
- Peak-to-peak jitter, or the distance from the smallest to the largest measurement on the normal curve. In most circuits, this value increases with the number of samples taken, theoretically up to a value of infinity. Under these circumstances, it is a not very useful measure.
- RMS (root mean-squared) jitter, or the value of one standard deviation of the normal distribution. Since this changes very little as the number of samples increases, it is a more meaningful measurement. However, it is only valid in pure Gaussian distributions. If any deterministic jitter exists in the distribution, the use of 1-sigma based on the entire jitter histogram for the estimation of probability of occurrence is invalid.
Multiple sources of random jitter add in an RMS fashion. To obtain total jitter,
a peak-to-peak value is needed to add random jitter to deterministic jitter.
Phase noise: the frequency domain
Phase noise is another measure of variations in signal timing, but the results are displayed in the frequency domain. Figure 2 shows a plot of an oscillator signal exhibiting phase noise.
Figure 2 -- Oscillator power spectrum
If phase noise wasn't present, the entire power of the oscillator would be focused at the frequency f = fo. However, phase noise spreads some of the oscillator's power to adjacent frequencies, which results in sidebands. In Figure 2, the sidebands are shown falling off at 1/fm for frequencies a reasonable distance away from the carrier. The fm frequency is the offset from the center frequency.
Phase noise is usually specified in dBc/Hz at a given offset, where dBc is the level in dB relative to the carrier. The phase noise of an oscillator at a given offset is derived from the ratio of the power in a 1-Hz bandwidth at the offset frequency to the total power of the carrier.
In Figure 2, phase noise is represented by the ratio of the area of the rectangle with 1-Hz bandwidth at offset fm to the total area under the power spectrum curve, approximately the difference in the height of the spectrum at the centre and at fm. The spectrum is the power spectrum of an oscillator with a noisy phase angle. The spectrum of these phase-angle fluctuations themselves can also be shown, as in Figure 3.
Figure 3 -- Phase fluctuation spectral density
The spectrum in Figure 2 is the power spectrum of the oscillator, and the spectrum in Figure 3 is the noisy phase angle term, called the spectral density of phase fluctuations. For offsets sufficiently far from the carrier, the phase noise in dBc/Hz measured from the power spectrum in Figure 2 is equal to the value of the spectral density of phase fluctuations in Figure 3.
The spectrum in Figure 3 is shown on a log-log scale, with phase noise sidebands
that fall at 1/fm2, or 20 dB/decade. In practice, there are regions in the sidebands where the phase can fall at 1/f3, 1/f2, and even 1/f0, depending on the noise process involved.
The 1/f2 region is referred to as the "white frequency" variation region, since it is due to white, or uncorrelated, fluctuations in the period of the oscillator. The behavior in this region is dominated by the thermal noise in the devices of the oscillator circuit. For low enough offset frequencies, the flicker noise of devices generally comes into play and the spectrum in this region falls at 1/f3.
Also worth noting: the sidebands in Figure 3 grow towards infinity as the offset frequency approaches zero. This is consistent with the behavior expected in timing jitter in free-running oscillators.
Translating between phase noise and jitter
As described earlier, jitter and phase noise characterize the same phenomenon. It can be useful to derive a jitter value from a phase noise measurement. This can be done as follows.
An oscillator has a phase noise plot, as shown in Figure 4. This plot identifies the band from 12 kHz to 10 MHz. The L(f) plot gives the sideband noise distribution in the form of a power spectral density function in units of dBc. The power level of the carrier is not important, since jitter reflects only the relative levels of phase noise (modulation) when compared to the "pure" carrier. The total noise power of the sidebands can be determined by integrating the L(f) function over the band of interest in this case, 12 KHz to 10 MHz.
Figure 4 -- Phase noise plot showing area of interest
These calculations yield the power level of the phase modulating (jitter producing) noise in this band. From this, we can determine the RMS jitter. The definite integral used is as follows:
The equation below can be used to determine the RMS jitter caused by this noise power:
This can be expressed in other units, such as Unit Interval (UI) or time. To convert to time, divide the above expression by the frequency of the carrier in radians, as follows:
As an example, the RMS jitter value for a 312.5-MHz oscillator can be calculated using the noise power values plotted in Figure 4. Integrating the phase noise curve for the 12 kHz-to-20 MHz interval yields a figure of -63 dBc:
The RMS phase jitter value in radians is therefore:
This jitter value in radians can be converted to RMS jitter in picoseconds:
The same 312.5 MHz oscillator will have a typical total jitter value in the region of 5 ps RMS. Consequently, the RMS jitter calculation of 0.72 ps RMS is a small proportion of the maximum jitter.
Minimizing phase noise and jitter on boards
There are two key techniques that can be implemented by board designers to reduce deterministic signal jitter:
Minimizing phase noise and jitter in chips
- Fully differential signaling Differential signaling conventions such as LVDS or PECL greatly reduce the effects of deterministic jitter. Any interference or crosstalk experienced on a signal path will also be picked up by its differential path. The high common noise rejection of such signalling systems tends to cancel out jitter.
- Careful track routing Wherever possible, avoid stray signals that may be imprinted on to the signal track as a result of crosstalk or interference. The tracks should be as short as possible, and should not cross paths carrying fast-switching digital signals. If a differential signaling system is used, the two paths should stay as close as possible to each other so as to take advantage of their inherent common mode noise rejection.
At the chip level, the following design techniques can be used to minimize jitter:
Minimizing phase noise and jitter in cell blocks
- Differential signaling Even if incoming signals are single-ended, it makes sense to convert to differential signaling on-chip for the same reasons described previously.
- Careful path routing Care must be taken in the routing of sensitive timing signal paths. Again, keep routes as short as possible and avoid crossing any digital tracks. Wherever practical, these paths can be screened. For instance, a metal-two path can be sandwiched between metal-one and metal-three plates, with both of the latter connected to a quiet ground.
- Choose a correct buffer size If a buffer is used to distribute the signal between blocks, care must be used to use the correct drive strength. Insufficient drive will result in a slow rising/falling edge, which is susceptible to noise pickup.
- Keep the substrate and ground quiet Substrate and ground noise are key contributors to deterministic jitter. In a chip with many synchronous digital outputs, ground bounce can reach several hundred millivolts, or even one volt. To keep ground bounce down, have as many power pairs as possible on the chip, preferably as close to the digital outputs as possible.
- Use a separate quiet ground It can be advantageous to separate the supplies for digital circuitry and sensitive analog circuitry, such as oscillators or PLLs. Power supplies for digital circuitry, particularly high-drive outputs, are highly susceptible to noise pickup, and can contribute greatly to jitter if used for timing circuitry. It may even be advantageous to use a supply filter for circuits such as PLLs to further reduce the effects of supply noise.
When designing cell blocks, the following techniques can be used to minimize jitter:
- Tail current There is a direct link between the current used in timing circuitry and phase noise. For example, increasing the tail current of a differential pair invariably leads to an improvement in jitter performance. There is thus a balancing act between reducing jitter and blowing power constrictions. Target the most sensitive circuits to selectively increase current where appropriate.
- Careful layout Care must be taken when laying out cells that could contribute to phase noise. It is important to lay out matching devices, such as inputs to a differential pair, as symmetrically as possible, and with the same orientation. This approach will subject the devices to the same process gradients, thus aiding matching. Resistors should be as wide as possible to reduce Delta W effects. If possible, the same type of resistor, and even the same value and size, should be used in the entire circuit to aid tracking across process and temperature variations.
In conclusion, to reduce jitter as much as possible, care must be taken at all design levels. In essence, high-speed digital designers should consider the effects of phase noise and jitter at every step of the design process.
Neil Roberts is a high-performance analog designer at Zarlink Semiconductor.