The transition from one air interface generation to the next, compounded by the rapid and constant changes of standards and protocols, makes the delivery of software defined radio (SDR) extremely desirable, but the practicality of creating a true SDR has been elusive.
Traditionally, the hardware structure of a handset is often defined years before deployment because the needed architecture flexibility to do otherwise is incompatible with today's conventional IC technologies. Because handsets are churned every six months to gain new features, the potential product modifications are left to the DSP/RISC software domain because costly ASIC designs create long lead times of six months to two years.
Meanwhile, the cellular industry lives in a very dynamic world. Consumers are becoming more mobile and frequently roam between networks, countries, and regions with heterogeneous structures. In building up a global presence, service providers are finding it simpler and easier to purchase existing networks than to erect new towers, many of which are not consistent with their existing networks. Due to the development complexities of conventional IC designs, deployment of third generation cellular is much slower then earlier forecasts, giving doubts about which technologies will prevail in five to eight years, such as CDMA2000, W-CDMA, 802.11, or Bluetooth.
Other factors include:
- Will these technologies continue to rapidly and substantially change?
- Could something completely different prove to be a dominant technology for areas like data services, like Ultra-Wideband (UWB)?
- Can SDR be implemented at reasonable cost with a reasonable die size?
More and more, there are many existing and overlapping wireless networks, including satellites, cellular, PCS, and radio. Because these changes and issues are not easily solved or even predicted, the end-users are the ones to feel the pain, many owning and operating multiple wireless products. Rather than separate products being developed for each network, one device should suffice for all requirements.
We believe adaptive computing tames this complex design beast, providing a software environment that quickly and painlessly changes the underlying handset architecture. The complex design issues become transparent to the end user and easier for developers to solve. Adaptive hardware can absorb changes in the air interface, such as CDMA, W-CDMA, GSM, TDMA; the numerous technical pieces such as multipliers, FFTs, RRC filters; the real-time environmental effects such as dynamic interference filtering; and new applications such as MPEG4 video and MP3 audio.
Using adaptive computing techniques, an SDR is not only feasible, but it can be designed and implemented in less time, with less design risk, and in less silicon area as compared to its ASIC counterparts. The result is lower overall cost, while enabling vendors to keep pace with changing market demands and trends.
Let's use a typical 3G handset as an example. Currently, products are created using a combination of hardware circuits, DSPs, microprocessors/controllers and ASIC accelerators. This combination is thought to bring the best of all worlds to bear. The software programmability of the DSPs and microprocessors bring overall ease-of-use, risk reduction, lower development costs, and greatly reduced time-to-market. The ASICs are used as hardware accelerators for higher performance gains and lower overall power consumption. A typical 3G handset design may have one DSP block, one micro-controller, and one to three million gates of ASIC accelerators.
This mixed-design concept is certainly valid, however, real world issues conspire to make it difficult to use. Because of cost constraints the DSP is always sized with very little performance headroom. Most protocol and standard changes usually require 20-50% more horsepower (vocoders) and cannot be upgraded into the latest generation DSP. More importantly, the ASIC implementation, the area in which most of the work is actually being done, cannot be changed.
An interesting analysis is to look at the total MIPS required for a typical 3G handset. It takes approximately 13,000 MIPS for both the application and baseband sections. Existing low-power DSPs, running at 200MHz,only reach 400 MIPS. The other 12,600 MIPS must still be supplied by the ASIC.
And, ASICs come with their own list of issues: long-lead design times, high cost, high risk, little overall re-use, and the need for highly skilled engineers. So, while the DSP gleans most of the attention due to its ease-of-use, low risk and design reuse benefits, the ASIC contributes the majority of the performance and low power consumption necessary to create a 3G handset.
In contrast, adaptive computing employs a new hardware architecture designed to supply the benefits of both the DSP's programmable software and the ASIC's low power consumption and high MIPS - all in a single chip. The adaptive computing structure is composed of heterogeneous nodes, with each node tuned to a different domain of computational problems, resulting in ASIC-class performance, as well as low power consumption.
The nodes are tied together by a data network, with the nodes and the buses adapting to a large variety of functions by means of software. Even larger functions are accomplished by grouping nodes together so that they share either logic capabilities or memory storage. The entire system, or any part of it, is modifiable in a single clock cycle.
Using the concepts of adaptive computing technology, QuickSilver's Adaptive Computing Machine (ACM) has been used to design and benchmark handset applications against existing ASIC and DSP solutions: CDMA2000, W-CDMA, MPEG4, MP3 and others.
Looking specifically at two compute intensive wireless areas CDMA2000 and W-CDMA searcher acquisition sections -- the benefits of an adaptive computing approach become readily apparent. These two designs have always made use of ASIC accelerators in order to meet the high performance and low power specifications necessary in a mobile, wireless handset environment.
A CDMA2000 searcher with 2X sampling, 512-chip complex correlations and captured data processed at 8X chip rate has a nominal ASIC performance of 3.4 seconds. Using macro adaptability, measured ACM results are 1.0 sec. The step 3 portion of the W-CDMA searcher at 1X sampling, 256-chip correlations with streaming data has an ASIC nominal spec of 533 microseconds, while the measured ACM performance is 232 microseconds.
Because an ACM is able to run at the maximum rate of the silicon, as opposed to the rate at which a fixed function ASIC can fit into the system design, the adaptive computing platform can do more work with the same silicon. In a conventional cellular handset, most of the ASIC/DSP components have little or nothing to do until system acquisition is complete. But in an adaptive computing-based platform, resources sitting idle can be reassigned to other tasks; in this example, accelerating the system acquisition process.
The adaptive computing approach showed three important benefits. First, the ACM outperformed best-of-breed ASIC solutions by a factor of three, a significant improvement to a user who may be waiting minutes once the phone is turned on to acquire a new cdma. Second, the same ACM ran both CDMA2000 and W-CDMA standards, without the need for dedicated hardware for either standard. And, all the designs were done in a purely "software" environment using a high-level language C++ derivative.