REGISTER | LOGIN
Breaking News
Design How-To

Hyper pipelining of multicores and SoC interconnects

NO RATINGS
Page 1 / 7 Next >
More Related Links
View Comments: Newest First | Oldest First | Threaded View
Tobias Strauch
User Rank
Author
re: Hyper pipelining of multicores and SoC interconnects
Tobias Strauch   12/4/2010 7:04:56 PM
NO RATINGS
I would be happy if I can explain it any further on the phone. You can also google for “C-clow Retiming” (as I have learned) to get further information. You basically get 2 processors (or any other core) for the size of 1.4 and 4 for the size of 2 whereas the behavior of each core doesn't change. The number gets more and more stable based on customer cases.

uanatol
User Rank
Author
re: Hyper pipelining of multicores and SoC interconnects
uanatol   12/3/2010 10:27:34 PM
NO RATINGS
The first pictures are crutial for the understanding of your idea and I am afraid I did not understand it from them, except that it can be used as a timing optimization technique for critical paths. I do not see what is its benefit for the multi-core designs to get better performance. It is a serialization and not a parallelization technique. The statement "the behavior of the sequential logic doesn't change", strictly speaking, is not correct. It changes at least the initialization sequence.

Tobias Strauch
User Rank
Author
re: Hyper pipelining of multicores and SoC interconnects
Tobias Strauch   11/11/2010 12:33:11 PM
NO RATINGS
I'm not sure if these modifications can efficiently be done on netlist oriented databases. The novel approach is, that the modifications are automatically done on RTL. 1) You have to use the hyper pipelined version as a new core in your design and verification process. It affects the surrounding logic as well. 2) You don't want the P&R-tool to do the modifications over and over again, because it is very time-consuming on netlist level. 3) In case you do an ASIC later on (the traditional way), you want to have identical RTL source. 4) The RTL version enables manual modifications after the automatic hyper pipelining process (for instance inter-processor communications). It is more a core based design tool. It is also used for ASIC-only projects. @jskull: Right, this idea has been around for years and designers doing this already quite naturally. In fact, I did my diploma thesis back in '98 on this. It was fun to remove the register again and run wave pipelining on datapaths and FSMs on the good old XC4000 devices. That was fun. Do you know why Xilinx didn't continue with this approach?

jskull
User Rank
Author
re: Hyper pipelining of multicores and SoC interconnects
jskull   11/11/2010 9:20:49 AM
NO RATINGS
This idea has been around for years. Xilinx were talking about 'C-slow retiming' in Virtex FPGAs back in 2002.

DrFPGA
User Rank
Author
re: Hyper pipelining of multicores and SoC interconnects
DrFPGA   11/5/2010 7:49:32 PM
NO RATINGS
I hope the big FPGA guys are looking into this as a possible add-on to their toolset. Any FPGA vendors want to provide some feedback?

Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed