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# Powering DDR memory and SSTL logic

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re: Powering DDR memory and SSTL logic
6/14/2011 2:36:59 PM
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The statement "Any useable system will need to have the outputs terminated" is not true. If you use a point-to-point memory interface with on board packages, short leads and controlled driving impedance's, parallel termination of data lines may be removed, saving considerable power and relaxing Vtt req's. The address/control bus will of course still need parallel termination for buses wider than one package.

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re: Powering DDR memory and SSTL logic
6/3/2011 7:38:10 PM
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Case 2) Calculating the additional VDD supply to power the I/O function, which is "Iout = 0A" in the datasheet VDDQ current specification. When calculating the additional VDD supply current, one must consider one half of each of the differential pairs because one of the pairs is sourcing current from the I/O supply (VDD) into the termination node while the other is sinking the same current from the termination node to ground. The currents cancel with respect to the termination node (they form a matched resistor divider) but there is still current flowing from VDD to VTT and from VTT to GND through the drivers of the differential pair and that current still needs to be sourced from VDD, even if it doesn't need to be sourced from VTT.

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re: Powering DDR memory and SSTL logic
6/3/2011 7:33:13 PM
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Case 1) Calculated the necessary termination current: When calculating the termination current (current sourced or sunk by the termination supply) Each differential pair is self-canceling since one line of the pair will source current and the other line sink an equal current. Producing a net 0 current.

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re: Powering DDR memory and SSTL logic
6/3/2011 7:31:15 PM
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Something went horribly wrong with the formatting in that post. I will try to correct and clarify in my next comment

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re: Powering DDR memory and SSTL logic
6/3/2011 7:29:22 PM
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Let Me See, There are 2 different cases for reviewing the output current needed. To calculate the source/sink current at the termination voltage however, the differential pairs alawys cancel as one of the pair sources current into the termination node and the other sinks current from the termination node, generating a net zero-current. However, to calculate the additional input current on the VDD supply, we need to consider that half of the differential pair strobe-lines will always source current into the termination while the other sinks that current. While these currents cancel from the termination node's point of view, they don't cancel from the I/O Supply.

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re: Powering DDR memory and SSTL logic
5/31/2011 11:28:17 AM
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Thanks for the article. I have a doubt wrt to this statement. "Reviewing the pin assignments of this device, we identify 16 data lines and up to eight differential strobe lines (if used) for a maximum of 20 terminations. We only consider half of the differential pair strobe lines since one is always low while the other is high." At one point you say a 1 and 0 would cancel out each other and draw no current. but when it comes to DQS/DQSX you are still counting half the number. Aren't they always 10 pair and so one doesn't need to count that current ?

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re: Powering DDR memory and SSTL logic
5/26/2011 8:08:33 PM
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Tony, TI also offers switch based VTT solutions in both internal MOSFET and external FET configurations, one is even mentioned in the article. Switched solutions are not always "better" they are different. They offer a small improvement in power consumption at the expense of increased cost, size and component count. For most applications where RMS current on the VTT rail below 1A, switching solutions save very little power. At 1A using DDR2, the savings is a mere 400mW if the switcher is 100% efficient!

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re: Powering DDR memory and SSTL logic
5/26/2011 7:52:07 PM
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TI's Vtt solution is LDO based with 50% efficiency. Enpirion's EV1340 4A and EV1380 8A Vtt's are switching solutions with higher efficiencies and a better solution with great ripple.

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re: Powering DDR memory and SSTL logic
5/26/2011 5:19:31 PM
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Dr DSP, The article is based on an Embedded Systems Conference - Silicon Valley 2011 presentation that I gave in May 2011. Since it was a conference paper, I tried to avoid marketing specific reference designs. The basic design will vary depending on the power levels needs, and currently most reference designs focus on the mid-current levels of 3-10A of VDDQ current & 1-2A of VTT current used by mobile computing solutions. An example of such a solution can be seen in the datasheet for the TPS51116 DDR Power Regulator from Texas Instruments.

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re: Powering DDR memory and SSTL logic
5/26/2011 4:09:33 PM
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Thanx for posting this article. Too many times memory articles focus on the timing of the interface and not on the power issues. This is a very useful overview. Now we just need a good reference design to pull it all together. Anyone know of a good one?

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