# Gray Code Fundamentals – Part 2

The term Gray code is typically used to refer to a binary sequence in which only a single bit changes value when transitioning between adjacent states.

In this, the second installment of our mini-series, we take a look at generating Gray codes and also Binary-to-Gray and Gray-to-Binary conversions.

Just to refresh our memories, in **Part 1** we considered the concept of Gray codes in general; in **Part 3** we will ponder the generation of sub-2^{n} Gray code count sequences; in Part 4 we will consider the generation of sub-2^{n} sequences with consecutive values; and in Part 5 we will take a leap into the unknown to wrestle with the concept of "n-ary" (non-Boolean) Gray codes.

**Generating a Gray code**

Before we start, let's briefly remind ourselves as to the difference between a standard binary count and one of the many possible Gray code equivalents as illustrated in Figure 2-1 (we'll use 4-bit sequences for the purpose of these examples).

Commencing with a state of all zeros, a Gray code can be generated by
always changing the least significant bit that results in a new state.
An alternative method which may be easier to remember and use is as
follows:

- Commence with the simplest Gray code possible; that is, for a single bit.
- Create a mirror image of the existing Gray code below the original values.
- Prefix the original values with 0s and the mirrored values with 1s.
- Repeat steps 2) and 3) until the desired width is achieved.

An example of this "mirroring process" used to generate a 4-bit Gray code is shown in Figure 2-2 (it might be more correct to call this a "recursive reverse-and-prefix" technique).

**Figure 2-1. Binary versus Gray codes (4-bit count sequences).**

**Figure 2-2. Using a mirroring process to generate a 4-bit Gray code.**

**Binary-to-Gray and Gray-to-Binary conversions**

It is often required to convert a binary sequence into a Gray code or vice versa. Such converters are easy to create and are of especial interest here due to their affinity to Reed-Müller implementations (I’ll do an article on Reed-Müller Logic after I’ve finished this mini-series on Gray codes). First let's consider a Binary-to-Gray converter as illustrated in Figure 2-3.

**Figure 2-3. Binary-to-Gray converter.**

The checkerboard patterns of 0s and 1s in the Karnaugh Maps immediately indicate the potential for Reed-Müller implementations. Similar checkerboard patterns are also seen in the case of a Gray-to-Binary converter as illustrated in Figure 2-4.

**Figure 2-4. Gray-to-Binary converter.**

**It's very quiet in here!**

Gray code counters are of interest for a variety of applications, such as representing the state variables in state machines or acting as pointers in First-In First-Out (FIFO) memories. This is because only one output bit is ever toggling at a time in a Gray code "counter", as opposed to possibly multiple bits in a binary counter.

In addition to preventing intermediate states, Gray code counters consume only half the power of an equivalent binary counter and they generate correspondingly less noise. Actually, while the power and average noise difference between a Gray and a binary counter asymptotically approaches two, the peak noise difference is equal to the number of bits, since a Gray counter toggles only one bit at a time while a binary counter toggles all of its bits simultaneously two times over the course of a full-count cycle with fewer bits toggling proportionally more times.

**Actually implementing a Gray code counter**

Before we proceed, let's briefly ponder the process of actually implementing a Gray code counter. Just to give us something to play with, let's suppose we wish to generate a Gray code that can be used to index into a memory array. For example, suppose we're implementing something sort-of like a FIFO, and that (for the purposes of this example), we simply wish to keep on cycling through all of the memory locations. The point is that we aren't particularly concerned as to the order in which we address the locations, just that we sequence our way through them visiting each one a single time before returning to the first location to do it all over again.

Assuming that we're dealing with a 16-word memory array, one scenario [as illustrated in Figure 2-5 (a)] starts with a standard 4-bit binary counter, in which the current count value is passed through a chunk of feedback logic to generate the next count value. Also, the current count value is passed through a Binary-to-Gray converter (as introduced in Figure 2-3) to generate a corresponding Gray code.

**Figure 2-5. Two techniques for generating a Gray code sequence.**

The alternative technique [as illustrated in Figure 2-5(b)] is to simply create a Gray code counter from the ground up. Now, if we were to compare the binary counter (including binary-to-Gray converter) with the Gray code counter, there are several things I don't know off the top of my head:

- How many logic gates are required for each implementation?
- How many levels of logic gates are there in the two feedback paths?
- What's the (relative) maximum frequency of each type of counter?
- What's the (relative) switching activity, noise, and power consumption of each type of counter?

I tell you, I'm constantly amazed by the number of things I don't know. Now, we could work this out, but I'm a tad busy at the moment, so we'll leave the pondering of these posers as an exercise for the reader (grin). Of course, if you do work all of this out, it would make the basis for a great follow-up article that I could post under your name here on Programmable Logic Designline.

But we digress… in

**Part 3**we will take a look at generating sub-2

^{n}Gray code count sequences.

**Author's Note:**The material presented here was abstracted from my book

**Bebop to the Boolean Boogie (An Unconventional Guide to Electronics) 3rd Edition**, with the kind permission of my publisher, Newnes (an imprint of Elsevier).

**About the Author**

Clive “Max” Maxfield is president of

**Maxfield High-Tech Consulting**and editor of the EE Times

**Programmable Logic Designline**. After receiving his B.Sc. in Control Engineering in 1980 from Sheffield Hallam University, Sheffield, England, Max began his career as a designer of central processing units for mainframe computers. Over the years, he has designed and built all sorts of interesting "stuff" from silicon chips to circuit boards and brainwave amplifiers to Steampunk “Display-O-Meters”. Max has also been at the forefront of Electronic Design Automation (EDA) for more than 20 years.

Max is the author and co-author of a number of books, including

**Bebop To The Boolean Boogie (An Unconventional Guide to Electronics)**,

**FPGAs: Instant Access**, and

**How Computers Do Math**.

Author

Max The Magnificent 2/17/2014 11:04:35 AM

i am a bit stuck on how to derive the state map for the conversion which i would then use to design the sequeantial circuit.I think there are two things here. let's say you have four registers that are used to hole your BCD count. Let's call them b3, b2, b1, and b0. So the first thing you need is a block of combinatorial logic in the feedback path to generate the next BCD value in the count sequence.

That is, you take the outputs from b3, b2, b1, and b0, feed them into your block of logic, and use the outputs from this logic to drive the inputs to your registers, so every time you get a clock pulse the BCD counter counts.

The next thing you need is another block of combinatorial logic that takes the outputs from the b3, b2, b1, and b0 registers and generates your 4-bit Gray code -- let's call these bits g3, g2, g1, and g0.

Take a look at my table -- let's start with g0. The only times this is a 1 corresponds to the BCD states of 1, 2, 7, and 8 (0001, 0010, 0111, and 1000). So we can say:

g0 = (!b3 & !b2 & !b1 & b0) | (!b3 & !b2 & b1 &!b0) | (!b3 & b2 &b1 & b0) | (b3 & !b2 & !b1 & !b0);

We would do the same thing for the other three Gray code bits (and we'd use the same technique to generate the next count value for the BCD feedback path).

Then use standard logic minimization techniques (like Karnaugh maps) to make the logic as small as possible.

I hope this helps. Let me know how you get on. Happy Monday! :-)

Author

BSc Student 2/16/2014 5:55:28 PM

Author

Max The Magnificent 2/16/2014 12:13:18 PM

I am to design a sequential circuit which converts BCD to Gray code. Hope you will be able to help.This is easy-peasy -- check out this blog -- here's the code:

DEC BIN GRAY

0 0000 0000

1 0001 0001

2 0010 0011

3 0011 0010

4 0100 0110

5 0101 1110

6 0110 1010

7 0111 1011

8 1000 1001

9 1001 1000

Tra Da!

Author

BSc Student 2/15/2014 7:35:00 PM

Author

JayD030 6/17/2011 7:31:03 PM

Author

davidlsimpson 6/9/2011 5:57:47 PM