# Charge-Pump Phase-Locked Loop—A Tutorial—Part II

**4. Frequency Response**

In this section we examine the frequency response of the CP-PLL. The effects of zero-pole placement in the loop-filter are examined in relationship to stability, peaking and jitter transfer.

**4.1. General PLL Gain**

The following model for the PLL in Fig. 4-1 explicitly shows the loop constants.

A simplified model for the PLL (Fig. 4-2) consolidates the individual loop constants into a single loop constant * k*.

Note that the transfer function * g*(s) in Fig. 4-2 is the open-loop gain of the system.

The open-loop gain is

The closed-loop gain is defined as

Substituting (4.2) into (4.3) yields

The phase-error gain is defined as

From which

**4.2 Desirable Filter Characteristics**

In section 3.3, we discussed the loop-filter transfer function (3.12). Here we further determine the suitable characteristics of the loop-filter regarding its ability to track changes on the input clock. First, we consider the response to a step change in phase of magnitude ?Ø given by

Taking the Laplace Transform of Ø_{i}(* t*) gives

The phase-error transfer function for this particular input is given by

Canceling terms yields

Applying the final value theorem yields

Thus, regardless of the type of loop-filter, there is no steady state phase-error when a step change in phase is applied to the input.

Now consider the response to a step change in frequency. This is of a practical concern for the following reason: when the input is removed from the loop, the VCO will operate at the VCO’s *free running frequency* *w*_{o}. The application of an input constitutes a step change in frequency of magnitude ?*w*.

The time-domain response to a step change in frequency of ?*w* * U*(

*t*)

Taking the Laplace Transform of Ø_{i}(* t*) gives

The associated phase-error gain is

Factoring yields

Applying the final value theorem yields

The resulting steady-state phase-error is

Equation (4.19) indicates that the steady-state phase-error for a step change in frequency does depend on the characteristics of ƒ(s). In particular, the phase error can be made arbitrarily small if the D.C. gain of ƒ(s) is very large. Thus the condition for zero steady-state error is given by

**Example:**

Consider the following two filters driven from a voltage source (Fig. 4-3). The D.C. gain of the passive filter is unity, indicating a nonzero steady- state error for a step in frequency. On the other hand, the active filter has infinite gain at D.C., ensuring zero steady state error.

It is for this reason that active filters are frequently employed in PLL designs where the loop-filter is driven from a voltage source. In the following section we consider a passive filter that is driven by a current source.

**Example:**

Now consider the passive filter driven by a current source (Fig. 4-4). The D.C. gain in this case is infinite. This is one advantage of the charge-pump PLL; that the D.C. gain can be made infinite using only a passive filter.

**4.3. CP-PLL Gain**

From (4.2) the *open-loop* gain for CP-PLL is

Substituting (3.13) for ƒ(s) into (4.2) yields

The corresponding closed-loop gain is

Substituting (4.21) into (4.22) yields

Equation (4.23) can also be expressed in standard form (4.24), however, we will find it more convenient to work with (4.23) instead.

Where the damping constant is

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