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New metric for phase-change memory

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R G.Neale
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re: New metric for phase-change memory
R G.Neale   1/9/2012 10:05:35 AM
Are the authors of this paper serious, when they introduce the precision measurement of time into the complexities of sensing in a phase change memory (PCM) array? They acknowledge the problems with this drift metric, capacitance; for which they proceed to offer a solution by adding a further level of complexity for compensation. I assume this compensation would also need to include the effects of temperature. There is a dearth of measurements at elevated temperature and with write/erase lifetime in this paper. The simplifying structural assumptions made at the start: the hemispherical bottom electrode and equating the dome to a flat surface, are proven by equation fitting from what appear to be device measurements at a single temperature. While this new drift metric might offer an interesting analytical tool for probing the internal structures of PCM devices for those without the analytical resources of IBM- I for one am not convinced it will amount to anything more than that in relation to commercial PCM products. It would be more interesting if IBM would devote some of their resources, as they do in their fig 1(a), for a single level, to an actual cross section of the dome in each of its four multilevel states. That would avoid the need for invoking some mysterious crystal filaments to explain anomalies. I would suggest that as the set current is reduced they should pay attention to the shape of the dome, especially along the dielectric surface adjacent to the bottom electrode. On the subject of scaling, again from figure 1, it is interesting that for a 15nm diameter electrode the width of the dome is 45nm, suggesting that in an array the nearest neighbors center-line must be at the very least 45nm away, questioning the advantage of the multilevel cell over the single level cell.

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