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Breaking through the embedded memory bottleneck, part 1

7/30/2012 04:48 PM EDT
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re: Breaking through the embedded memory bottleneck, part 1
DaveWyland   8/2/2012 6:04:30 PM
We are being reminded that a CPU is a memory controller. Its function is to read data, combine it and write it back, using an instruction stream from the same (von Neumann) or a different (Harvard) memory. The performance of the system is ultimately determined by the memory, once the CPU has been optimally designed for its task universe. And CPU architectures have stabilized at the Pentium style of ~2.5 instructions/clock. Given the CPU design, system performance is limited by MOPS x Number of memories. An N-port memory looks like N memories, but the performance starts dropping off for N greater than 2. I have some experience with this, having worked on dual and quad port memory designs. Multi-port is useful, not a panacea. IMO, we are being dragged kicking and screaming into the land of data flow processing. This is where you have chains of processing nodes that crunch data that flow through them, assembly line style. You have small nodes, each with its small memory, and lots of them. This lets you multiply memories (N much greater 1) and thereby multiply system performance. The fact that each node is small in both memory size and processing logic helps, too. The pain is that your algorithm is now in the wiring of nano-sized processing chunks. And you may want some chunks to be different than others. Also, you have to have a system of hardware that lets you do this flexibly and tools that let you create and debug this wired-chunk algorithm design. Two thoughts come to mind. FPGAs are now good candidates for the hardware. They now have HUGE capability and software for wiring them up, by definition. And graphic data flow systems such as Matlab/Simulink and Labview are successful in making such systems. We will have to change our way of designing computer systems if we want more performance. OTOH, it is possible.

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