For storage capacitor scaling, metal-insulator-metal (MIM) capacitors require the specific capacitance corresponding to an equivalent SiO2 thickness of sub-1 nm, high-k dielectrics, extremely low leakage current, and a highly conformal deposition method. An ultra-thin Al2O3 layer added between ZrO2 layers, with W/TiN electrodes is a key solution for 3x nm cells. All the major manufacturers achieve this challenge by adopting the same multi-layer stack of TiN(Plate)/ZrO2/Al2O3/ZrO2/TiN(Bottom Electrode) called a ZAZ TIT capacitor as shown in Figure 2.
Figure 2: Memory cell capacitor plate/dielectrics of each device. The TiN/ZrO2/Al2O3/ZrO2/TiN (ZAZ-TIT) capacitor structure with ultra-thin uniform Al2O3 layer between ZrO2 layers is a key challenge for 3x nm technology node.
A thin Al2O3 layer is inserted between ZrO2 layers to suppress leakage current. The physical thickness of the dielectrics on the 3-D cylindrical capacitor node is another major challenge to further scaling. Most of the 3x nm DRAM cell capacitors use multi-layered dielectrics with about 7 to 9-nm thickness in total, which means further scaling down of physical dielectric thickness is desperately needed for future 1x nm DRAM cell architectures.
A SiGe layer is used on the TiN top capacitor plate with the exception of Micron/Nanya which uses a tungsten (W) layer. SK-Hynix uses double layered poly-Si plugs to connect storage node with drain region, while Elpida uses double layered W/TiN and poly-Si plugs. The height of the cell can be increased by using a Mechanically Enhanced Storage Height (MESH) structure to support the capacitor. Samsung, SK-Hynix and Elpida use single nitride layer for this, while Micron/Nanya uses double nitride layers to support cylindrical capacitors. An estimation of cell capacitance suggests the SK-Hynix SDRAM cell has larger cell capacitance than the other devices.