Geneva -- STMicroelectronics is targeting the new generation mobile terminals, cellular infrastructure equipment, networking, broadband modems, voice-over-IP, data storage and mobile multimedia for its new embedded dual-MAC DSP core that can run at above 600MHz or consume less than 0.1mW/MMAC (Million MAC) in a typical portable telecom application.
Available in the form of synthesizable IP, the ST122-DSP can be mapped into various versions ranging from ultra-low power to high speed operation.
Based on ST's ST100 DSP architecture that allows user- customized instruction sets, the ST122 Dual MAC core is supported by an evaluation chip fabricated in 130nm technology and a complete development platform.
Like all cores based on the ST100 architecture, the ST122 core combines VLIW and RISC features to achieve the best balance between performance and code size, according to ST. Flexible instruction modes allow a mixture of 16, 32 and 128-bit instructions and instruction sets can be customized to add applications- specific operators. Custom extensions have demonstrated an important performance boost in ADSL, GPRS/EDGE, audio and video algorithms while adding minimal silicon overhead. Custom instructions are controlled through the ST100's tightly coupled co-processor extension interface and are fully supported by the ST100 DSP tool chain.
To support the most demanding performance needs the new dual-MAC ST122 core can fetch four 32-bit instructions using 128-bit instruction mode and execute them in a single clock cycle. High performance is the result of ST's advanced digital design techniques and a unique architecture design feature that enables direct memory access at CPU speeds. Highly efficient memory interfaces allow the connection of a large amount of flat data memory. The ST122 evaluation device includes 16Kbytes of L1 Program cache, 256kBytes of L2-Program memory and 2x64Kbytes of data memory accessed at the DSP core's maximum clock speed.
Designed for easy and optimal integration into complex system-on-chip products, the ST122 is supported by a full range of peripherals. Configurable plugs supporting AMBA bus from ARM or specific fast access ports make it easy to interconnect efficiently multiple DSP and MCU cores in SoC devices. Multicore debug is fully supported in such cases.
The ST122 core, peripherals and configurable interfaces are all synthesizable soft IPs available for easy physical integration in application chips. ST can also provide ST122-DSP subsystems as optimized hard macros ready on demand.
"Today the challenge facing equipment manufacturers is to add new functionalities while reducing cost, and this can only be achieved by super- integrating DSP cores, MCU cores, memories and other functions into a single SoC chip," explained Jean-Claude Michalina, General Manager of ST's DSP and Micro Division.
Software development is supported by an integrated software tool chain which includes a highly-optimizing C compiler providing best-in-class performance and code size, plus advanced system modeling tools, easy program build with graphical interface, code profiling facilities and multi-core debugging.
The ST122-DSP is embedded in STMicroelectronics products that will soon be introduced to the market. It is available for licensing to customers and partners.