Lattice Semiconductor Corporation introduced its revolutionary new family of ispClock in-system programmable clock generator devices. The first devices in the ispClock5500 family, the 10-output ispClock5510 and 20-output ispClock5520, combine a high- performance clock generator with a flexible, Universal Fan-out Buffer. The on-chip clock generator can provide up to 5 clock frequencies ranging from 10MHz to 320MHz using a high-performance PLL and clock multiply and divide facilities. The Universal Fan-out Buffer can drive up to 20 clock nets using either single-ended or differential signaling, with individual output control for improved signal and timing integrity.
The new devices provide an unprecedented level of performance and flexibility in support of high-performance clock network designs on electronic circuit boards. The new product family marks the first application of Lattice's programmable mixed signal technology to the clock integrated circuit market, estimated at $1 billion and projected to grow at a 20% annual rate over the next four years.
First Single-Chip Solution for Entire Clock Tree Design
Within the devices, seven 5-bit counters (input, feedback, and five output) provide fine granularity in output frequency selection. The high-performance Universal Fan-out Buffer has a maximum pin-to-pin skew of 50ps regardless of bank and frequency, while the maximum cycle-cycle (peak-peak) output jitter is less than 100ps. The output skew of each clock net can be further controlled in delay increments of 200ps (lead or lag) to compensate for differences in circuit board clock network trace length. In addition, both the reference input and the Universal Fan-out Buffers can support a wide variety of popular single-ended and differential logic standards (LVCMOS, LVTTL, HSTL, SSTL, LVDS, LVPECL) at a variety of voltage levels. The input termination and output impedance of each output can be individually tuned to match each trace impedance, resulting in clock nets with high signal integrity.
"Lattice is extending the benefits of integration, in-system programmability and superior performance to clock management," said Stan Kopec, vice president of corporate marketing for Lattice Semiconductor. "Historically, clock networks were designed using multiple devices with limited functionality at various levels of the clock hierarchy. The new ispClock devices are the first products that conveniently and accurately solve the entire clock tree design problem with a single chip."
A Comprehensive Improvement Over Traditional Clock Network Design
Clock networks are traditionally designed using simple components such as fan-out buffers, clock generators, delay lines, zero delay buffers and frequency synthesizers. Timing errors due to unequal PCB trace lengths are addressed by using trace length matching through serpentine trace layouts. Trace impedance mismatch is frequently mitigated by trial and error selection of series resistors.
In contrast, ispClock5500 devices compensate for timing errors due to different trace length clock nets through a programmable skew feature, match trace impedances with output impedances by programming each output characteristic, and reduce EMI by programming output switching speed or slew rate. This results in board space savings, improved signal integrity, a simpler clock net hierarchy, improved timing convergence and lower cost.
The ispClock5500 devices' ability to store up to four timing and output configurations and easily switch between them further extends their utility by supporting easy clock margining (operating a circuit board at higher than typical frequency to evaluate design robustness) and power management (conserving dynamic power consumption by "downshifting" to a more efficient, lower frequency when performance is less critical). In-system programmability via the on-chip boundary scan port helps debug complex timing problems and tune individual network timing for best performance.
PAC-Designer Version 3.0, Lattice's PC-based mixed signal design tool, provides simple and intuitive pull-down menus for configuring all programmable features of the ispClock5500 devices. In addition, utilities such as a Skew Editor, Frequency Calculator and Frequency Synthesis support easy configuration of various counters while operating the PLL in its optimal operating range. Design configurations can be downloaded quickly into ispClock5500 devices via the PC parallel port. This version of the software can be downloaded for free from www.latticesemi.com
Pricing and Availability
Prices for the ispClock5520 device start at $18.25 in 1000 piece quantities. The device in a 100-pin TQFP package is available immediately in both commercial (0C to +70C) and industrial (-40C to +85C) temperature grades. PACsystemCLK5520 evaluation kits are also available through authorized Lattice distributors or on the Lattice Web site for $349.