LONDON STMicroelectronics has developed an innovative on-chip interconnect technology targeted at SoC designs. The patented ST Network on Chip (STNoC) technology, dubbed “Spidergon”, builds on the company’s existing on-chip communications expertise.
ST says an effective NoC architecture will be a crucial precondition for cost-effective SoCs targeted at convergence devices and, in particular, NoC technology will play a major role in improving design productivity. It says its interconnection topology, will deliver significant cost/performance advantages compared to other NoC topologies.
STNoC addresses one of the most critical issues in SoC technology, the interconnection between the many IP blocks that make up the SoC device. Typically, these include one or more high performance processor cores as well as complex, dedicated IP blocks such as audio/video codecs, a wide range of connectivity IPs (USB, Ethernet, serial ATA, DVB-H, HDMI etc), and memories. Up till now, the interconnection between these blocks has been implemented via traditional circuit-switched buses but it has been widely accepted in recent years that a new interconnection methodology is required to develop SoC devices that contain a billion or more transistors organised in tens or even hundreds of IP blocks.
Alessandro Cremonesi, vice president and deputy general manager, Systems Technology, at STMicroelectronics acknowledges there are several potential approaches to breaking this bottleneck, and that the existing NoC topology will be “good for a few more years before it runs out for steam.”
Cremonesi notes that in the long term, techniques such as optical intra-chip communications, in which ST has already reported world-leading R&D results, may eliminate the bottleneck problem. However, in the medium term, new intra-chip interconnection technologies will be required to maintain the combination of price/performance/power improvements required by customers, and that most in the industry acknowledge that NoC technology will be the best approach.
In the proprietary “Spidergon” topology, all of the IP blocks are arranged in a ring and each IP block is connected to its clockwise and its counter-clockwise neighbour as in a simple polygonal ring topology. In addition, each IP block is also connected directly to its diagonal counterpart in the network, which allows the routing algorithm to minimise the number of nodes that a data packet has to traverse before reaching its destination.
A major benefit, according to ST, is that this approach corresponds to a simple planar implementation where the wiring only needs to cross itself at one point, delivering the best possible price/performance trade-off.
ST suggests that topologies such as 2D-mesh that theoretically provide high communications speeds are expensive to implement in silicon because of their large number of router ports and connections; moreover the theoretically-offered connectivity can not be fully exploited in the on-chip domain due to the nature of communications traffic in real embedded applications.
Simpler topologies such as rings are cost-effective in terms of manufacturing cost but deliver relatively poor intra-chip communication speed, especially as the number of IP blocks in the SoC increases, as it is certain to do in all application scenarios.
“For some time, the semiconductor industry has accepted that the future of SoC lies in NoC. The issue for SoC manufacturers is to deploy this emerging SoC design paradigm in an industry that is dominated by the need to minimize silicon area and design cycle times,” said Cremonesi.
“With our Spidergon topology, we can freeze IP blocks into our libraries and put together any combination of IP that our customers require in a “plug and play” manner to rapidly develop SoC devices that deliver the industry’s best combination of price and performance.”
He stresses the most important feature of the Spidergon architecture is that the conceptual simplicity of the topology also translates into the most cost-effective silicon implementation of the key components: routers and network interfaces.
The technique is also said to lead to a reduced set of homogeneous building blocks with well-controlled configurability, allowing for a substantial reduction in verification time and easier maintenance, support and integration, all key strategic requirements.