This year's Design Automation Conference won't be focused on some hot new EDA market segment, like design-for-manufacturing or electronic system-level design. The real message of DAC 2007, convening in San Diego next week, has to do with fixing bottlenecks and filling gaps in the IC design flow.
A number of technology announcements will address problems that IC designers face every day. Functional verification, for example, is getting more automated, with new technology for test generation and quality assurance. Static timing analysis is making a leap in speed and capacity through multithreading and incremental capabilities.
DAC 2007 will bring new verification and electronic system-level (ESL) synthesis support for the multivoltage designs that are becoming commonplace in low-power flows. IC implementation will be updated with 45-nanometer placement and routing features, new design rule check and layout-vs.-schematic capabilities, and added design-for-manufacturing (DFM) functionality.
This year's DAC isn't just about digital IC design, either. There will be some activity in analog and custom design, and several announcements will target co-design of chips, packages and boards.
The concept of the "intelligent testbench" will edge a little closer at DAC. Startup Breker Verification Systems, for example, claims its Trek is the first commercial graph-based functional test synthesis tool. Trek lets users develop a verification plan, from which it automatically generates test vectors. In so doing, it promises to reduce the overall IC verification effort--in terms of head count, code size and time spent--by a factor of 10 or more, while ensuring 100 percent verification plan coverage.
Trek provides a presimulation analysis of the verification plan, synthesizes functional test vectors and then provides postsimulation analysis to show what was covered. "We think about requirements and generate functional test vectors from that plan," said Breker founder Adnan Hamid.
Another startup, Certess Inc., will demonstrate Certitude, a functional qualification software product for companies developing systems-on-chip or integrating intellectual-property (IP) blocks.
Certitude promises to go far beyond today's code-coverage and functional-coverage metrics by "certifying" that any bugs have been found. The tool uses a technology called "mutation analysis" to find weaknesses in verification environments. In one use model, it lets users trace back from undetected mutations, or changes, in HDL code to identify missing elements in the functional verification environment. In another, it provides an objective measurement of design quality.
Cadence Design Systems Inc. is attacking verification bottlenecks. A new release of its Incisive Formal Verifier speeds formal analysis by five to 10 times, while a "hot swap" capability between Incisive simulators and the Xtreme III accelerator achieves up a 10x to 1,000x hardware speedup. Cadence is also offering new assertion-based products for AHB, AXI and OCP standard protocols.
German formal verification provider OneSpin Solutions GmbH will tout what it claims is the first complete multiconfiguration verification solution. An extension of the company's 360 MV tool promises complete verification for configurable IP blocks.
With runs that can last for many hours, static timing analysis has become a bottleneck for many IC design teams. Startup CLK Design Automation Inc. is offering Amber, a static timing and signal integrity analyzer that takes advantage of multicore, multiprocessor compute platforms. CLK devised a nonblocking database, which means processors are never idle. With 16 CPUs, Amber can run 14.8 times faster than it does on a single CPU, said Isadore Katz, CLK's founder. Moreover, he said, Amber's incremental timing and signal integrity capability means it can run hundreds of times faster than tools that must rerun an entire analysis with every change.
CLK is not alone. Extreme DA this week will introduce GoldTime, a multithreaded static and statistical timing analyzer that runs on multicore CPU platforms (see story, page 45). Originally a specialist in statistical timing, Extreme DA is now focusing on "signoff" timing, said CEO Mustafa Celik.
Many IC designers are implementing low-power designs, but they're struggling with techniques such as multivoltage design and power gating. EDA companies are answering the call for better tools. Among the new offerings is href="https://www.eetimes.com/showArticle.jhtml;?articleID=199700380">MaVeric, a multivoltage verification solution from ArchPro Design Automation Inc.
Working from RTL input, MaVeric provides architectural profiling that tracks multivoltage states, transitions and sequences. It then generates multivoltage assertions and tracks coverage during simulation. It also produces voltage-aware functional specifications for cells and IP blocks, and it verifies power management in the context of the overall system architecture, ArchPro claims.
ChipVision Design Systems recently announced a low-power ESL synthesis technology that produces synthesizable RTL code from SystemC, ANSI C or C++ input. For a small area penalty, it is said to deliver a pre-RTL dynamic-power savings of up to 75 percent, and to shorten time-to-results by a factor of 60 compared with existing low-level approaches. The company expects to roll out products based on the technology late this year.
Cadence recently added a Low-Power Methodology Kit, which supplements its tools with a wireless "representative design" implemented using multisupply-voltage and power shutoff methods. The design comes with sample IP. The Cadence kit includes scripts, methodology documents and flow checklists.