An automated pre- and post-silicon memory test and repair tool supports repairable or nonrepairable embedded memories. The DesignWare STAR Memory System from Synopsys, which targets 20-nm and FinFET-based designs, detects new memory defects, including process variation and resistive faults. The offering includes automated SoC integration and verification, as well as hierarchical architecture delivering up to 30% reduction in memory test and repair area compared to the IP’s previous generation.
The system’s capabilities also can reduce the time required for silicon bring-up and defect analysis for yield optimization, shortening the ramp time to volume production. In addition, the design tool allows at-speed test and repair of high-performance processor cores by using a preconfigured test bus, which provides access to the memories inside the core in test mode. The system uses this bus to test memories and adds memory test and repair logic outside the IP core to avoid any impact on processor core performance.
The system comprises:
- Configurable test and repair register transfer level (RTL) IP
- Design automation tools for automated insertion of RTL IP and verification testbench generation
- STAR Yield Accelerator for automated generation of tester ready patterns in WGL/STIL/SVF, test algorithm programmability, and post-silicon failure diagnostics and fault classification
- STAR Silicon Browser for interactive silicon debug of memory using a PC or workstation
For more information, visit www.synopsys.com/bist
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