It seems to me that the folks at Lattice Semiconductor have a lot to brag about at the moment. A few weeks ago they announced a new programmable family of mixed-signal Platform Manager Devices (Click Here for more details); and now they have just unveiled their new 65nm flash-based MachXO2 PLD family.
On the one hand MachX02 devices are CPLDs; on the other hand they are poised to compete with low-end FPGAs and even small ASICs and ASSPs... but I'm getting ahead of myself...
The CPLD market is currently running around $600M a year. In recent times, this market has pretty much been dominated by three players: Altera with their MAX II devices, Lattice with their MachXO family, and Xilinx with their CoolRunner-II components. In fact Lattice has steadily been gaining market share and is currently the #2 player in this market (see Figure 1 below).
With the announcement of their new MachX02 devices, Lattice seem set to gain even more market share in the very near future (Alpha samples are available today, with engineering sample devices scheduled to be available in December 2010 and production devices available in March 2011).
But wait, there’s more, because – as we shall soon discuss – 65nm MachX02 PLDs deliver 3X increase in logic density, 10X increase in embedded memory, more than a 100X reduction in static power, 30% lower cost compared to their predecessors. This means that these devices can now compete in the low-end FPGA market against Actel, Altera, and Xilinx with their IGLOO, Cyclone, and Spartan offering’s respectively. (For example, traditional CPLDs tend to top-out at around 2K LUT, but MachX02 PLDs can contain up to 7K LUTs.) This is another $600M market, which means that MachX02 PLDs now have a $1,200M market to play in.
Figure 1. CPLD market share
(Source: Northland Securities and Lattice Estimates)
And there’s still more, because with prices starting as low as $0.75, static power as low as 19uW (yes, that is microwatts, NOT milliwatts), and hardened IP such as I2C, SPI, oscillators, and timer/counters (all of which can be completely powered off if not required)… this means that MachX02 PLDs may even compete with small ASICs and ASSPs, in which case the sky is the limit with regards to a potential market.
Hmmm, I wonder if these devices could be used in Pico Projectors (Click Here
to see my blog on these little beauties and Click Here
to see the associated design article from Lattice).
There are actually a lot of interesting things to note about these devices. For example note the triple-staggered I/O (depicted in the left-hand image below), which allows Lattice to increase the number of I/O. Also, observe the rather clever asymmetrical banking scheme (depicted in the right-hand image below). This allows designers who wish to use a larger number of I/O standards to maximize their I/O usage.
And speaking of I/O, the use of the lowest-cost BGA packages (as illustrated below) also serves to reduce the cost-per-LUT.
And the good news just keeps on rolling, because these little beauties support 3.3V, 2.5V, and 1.2V operation and – with an on-chip voltage regulator – they easily operate off the first power rail up (their sub 1ms instant-on ensures precise control during boot-up, while input hysteresis provides noise immunity for slow-rising inputs).
Also, on a personal note, I really like the image they use to depict the fact that MachX02 devices are “Do-it-All-PLDs” for high volume, cost sensitive designs – note especially the toothbrush, which I take it to imply that using these components will give us whiter teeth and brighter smiles (grin).
OK, what follows is the official announcement from Lattice:
Built on a low power 65-nm process featuring embedded Flash technology, the MachXO2 family delivers a 3X increase in logic density, a 10X increase in embedded memory, more than a 100X reduction in static power and up to 30% lower cost compared to the MachXO PLD family. In addition, several popular functions used in low-density PLD applications, such as User Flash Memory (UFM), I2C, SPI and timer/counter, have been hardened into the MachXO2 devices, providing designers a “Do-it-All-PLD” for high volume, cost sensitive designs.
A video demonstration of the MachXO2 PLD Family can be viewed here:
English - http://www.latticesemi.com/xo2videoen“Through the use of 65-nm embedded Flash technology, we have reduced costs and increased functionality for our traditional customers in the computing, industrial and telecommunication infrastructure markets, while dramatically reducing power consumption for designers of consumer equipment,”
Chinese - http://www.latticesemi.com/xo2videocn
Japanese - http://www.latticesemi.com/xo2videojp
said Gordon Hands, Director of Marketing for Low Density and Mixed Signal Solutions. “Many early access customers are already evaluating and designing with MachXO2 devices in a broad range of applications.” Three product options for maximum flexibility
The MachXO2 family offers three options for maximum flexibility. MachXO2 ZE devices range from 256 to 7K look-up tables (LUTs), operate off a nominal 1.2V power supply, and support system performance up to 60MHz. With power specified as low as 19uW and packages as small as 2.5mmx2.5mm, the MachXO2 ZE devices are optimized for cost-sensitive, low power consumer design applications such as smart phones, GPS devices and PDAs.
MachXO2 HC devices range from 256 to 7K LUTs, operate off a nominal 3.3V or 2.5V power supply, and support system performance up to 150MHz. Offering up to 335 user I/O and a robust design solution (instant-on, non-volatile, input hysteresis and single-chip), these devices are ideal for control applications in end markets such as telecommunications infrastructure, computing, industrial and medical equipment.
MachXO2 HE devices range from 2K to 7K LUTs, operate off a nominal 1.2V power supply and support system performance up to 150MHz. These devices are optimized for power sensitive system applications.Reaction from early access customers“For the last two years, we have used MachXO PLDs in our CCTV video over fiber optic multiplexers because they deliver compelling system integration benefits combined with a flexible and cost effective architecture,”
said Mr. Zhu Guangxin, Vice President of Engineering at Obtelecom. “For our next generation products, MachXO2 PLDs will enable us to provide more features to our customers at lower prices.” “We have been actively designing with MachXO2 devices and will be using them in our CNC (computer numerical control) products,”
said Mr. An Luping, R&D Manager at KND CNC Technique. “The unique system integration benefits of the MachXO2 family, such as hardened I2C / SPI functions and User Flash Memory, combined with low power consumption and attractive price points, allow us to use these devices as alternatives to high risk and expensive discretes, ASICs and ASSPs.” Free design tools and free reference designs accelerate development time
Customers can start designing with MachXO2 devices today using Lattice Diamond v1.1 software, which can be downloaded for free from the Lattice website (Click Here
Existing ispLEVER software users have the option to use the free ispLEVER v8.1 SP1 Starter software, downloadable from the Lattice web site, with an installed control pack (Click Here
In order to enable quick and efficient design and deployment of commonly used functions in system and consumer applications, more than 20 reference designs using MachXO2 devices can be downloaded for free from the Lattice website (Click Here
In addition, Lattice plans to make available two development kits that accelerate the evaluation of MachXO2 devices (Click Here
).Pricing and availability
MachXO2 LCMXO2-1200ZE and LCMXO2-1200HC devices are now available as Alpha samples, with engineering sample devices scheduled to be available in December 2010 and production devices available in March 2011. Pricing for the LCMXO2-256ZE/HC TQFP100 is $0.75 and the LCMXO2-1200ZE/HC TQFP100 is $2.00, both in 500KU volume. All members of the MachXO2 family are expected to be shipping in production by the end of Q3 2011.