NEW YORK — The semiconductor industry needs to embrace chip stacking amid a slowdown in Moore’s Law and the rise of data-driven applications, says an IBM fellow.
IBM is looking for alternatives to CMOS technology and Von Neumann architecture. Semiconductor packaging of integrated bipolar silicon is needed. In addition, 3D integration allows for strong I/O performance; 2.5D and improved materials are also highly beneficial as IBM looks for cost-effective means of semiconductor packaging.
Jon Casey, an IBM Fellow in the semiconductor research and development center, has a background in semiconductor packaging, which is involved in coming up with ways to augment the technology beyond Moore’s Law -- the theme of Casey’s presentation this week at the SEMI Industry Strategy Symposium in Half Moon Bay, Calif. Casey spoke with EE Times before the event and offered an overview of his speech.
Casey told us his views are relatively consistent with those of Bernie Meyerson, as expressed in Meyerson’s recent interview with EE Times. Casey began by saying that Moore’s Law and the traditional CMOS approach is severely challenged:
There’s been lots of press out there that says that Moore’s Law is dead or soon to be dead, and people are putting dates on that. The IT industry itself is undergoing a major paradigm shift to new architectures that are really data-centric due to the vast amount of data on those systems.
As a result, Casey noted the need for a change in approach.
We need to do things differently from how we’ve historically been doing them in CMOS. Our traditional systems really are not designed to handle massive amounts of data coming in at high rates. A lot of that data is quite uncertain, meaning there’s a lot of data that you want to ignore, the source of which you don’t know. The traditional MCU approach and Von Neumann architecture for systems are not designed to do that. We need to look at alternative ways to do that.
Casey indicated that semiconductor packaging of integrated bipolar silicon is revisiting that same area of technology.
Transitions to 450 and to EUV will happen when it is economically feasible to have happen. It’s a combination of factors that are needed. You start doing volumetric or heterogeneous scaling at the silicon packaging level to cheap performance gains to augment what we get from scaling moving forward.
Among the best ways to accomplish that is 3D integration. According to Casey, 3D provides exceptional I/O performance.
Traditional 3D stacking of two active chips, we believe, will be a beneficial approach moving forward. First of all, you get a tighter density; and second, if you step back and look at a data-driven architecture, the key feature is you need to access it quickly and optimize for I/O capability.
One way to accomplish that is to improve the materials, as well as the way the components are integrated and pulled together as closely as possible, according to Casey. “In short, communication distance equates to latency. What we are trying to do is scaling. 3D is a good approach to that.”
Then there is the option of 2.5D integration, an increasingly enticing one for IBM.
2.5D integration can be silicon-based, organic-based, or glass-based. We are in the process of evaluating those capabilities to deal with large workloads and large datasets. If you step back and look at the technical approach to this, there’s a lot of stuff IBM’s been doing.
Casey noted 2.5D solutions' ability to integrate chips from vastly different technologies to produce a module that has high performance at a good cost. He mentioned the use of a model with three chips, the first of which is a 45 nm SOI control chip with a CMOS processor die. It is placed on a 2.5D solution immediately next to that 45 nm CMOS processor die, where there are two 130 nm SiGe transceivers all placed on a silicon interposer on a substrate.
Now what you have is a module with three die on a silicon interposer. Now we have a functional transceiver with mixed silicon technology. The data rate between the chips is two terabits per second, which is very high. To integrate without using the highest level of silicon creates a solution that is independent of the success of Moore’s Law. That’s the thrust of the presentation: How do we get performance if Moore’s Law starts slowing down?
In closing, Casey said semiconductor technology is currently healthy. “It’s not going away. We need more and more devices. We need to figure out the most cost-effective way to move forward.”
— Zewde Yeraswork, Associate Editor, EE Times