I just received a jolly interesting email from Victor Lyuboslavsky about a really useful and free online tool he developed called EDA Playground. Victor's message reads as follows:
Hi Max, as a follow-up to our earlier communications, I just wanted to let you know that you can now simulate and synthesize SystemVeriog and other HDLs from a web browser on EDA Playground. Since the tool is free and online, there is nothing to install, and it runs on any OS.
Before I go into detail as to what EDA Playground offers, let me first explain why I created it. Not long ago, I was preparing myself for job interviews and trying to ramp up on SystemVerilog and UVM (Universal Verification Methodology).
I used the web to find code examples and tutorials. However, often the examples were incomplete. Sometimes they were missing the necessary code to hook the example into a real design. Other times, the code examples had syntax errors -- I might be presented with a working design, with lines stripped out, but with undefined variables and dangling commas left in. Other times the code examples simply did not work on my simulator. All this resulted in endless frustration for the student in me. I knew there had to be a better way, so I created EDA Playground.
EDA Playground is a free web application that allows users to edit, simulate (and view waveforms), synthesize, and share their HDL code. Its goal is to accelerate the learning of design and testbench development with easier code sharing and with simpler access to simulators and libraries. EDA Playground is specifically designed for small prototypes and examples (it is not intended to be used for a full-blown FPGA or ASIC design).
The usage model is simple -- type in your code, select your favorite simulator or synthesis tool, and click run. If your simulation dumps waves, all you have to do is click a checkbox and the waves will open in a new window after the run. Any code or waveform display may be saved as a static HTML link, like this example, so that anyone can open up the code, re-run it, and get the same result.
Currently, EDA Playground runs open source and/or free simulation and synthesis EDA tools. It supports several HDLs such as SystemVerilog, VHDL, MyHDL, and Migen. Verification engineers may play with several libraries and methodologies, such as UVM, OVL, SVUnit, and cocotb. UVM is currently one of the most popular verification methodologies. Here is a simple Verilog design and UVM testbench. For synthesis, EDA Playground uses the open source Yosys and VTR flows.
Most users are using EDA Playground for quick prototyping and simply trying something out. Some are using it to provide code examples when asking and answering questions in online forums. We have one engineer who uses EDA Playground during technical interviews to test candidates' HDL coding and debug skills. Another user, Neil Johnson, a guest blogger for EE Times, has been creating hands-on tutorials for the SVUnit library on EDA Playground.
We are currently working with universities to create hands-on web-based tutorials and labs that will be used in actual digital design university courses. Our vision is for EDA Playground to become the destination for HDL examples and best practices in the industry. We also plan to add more tools in the future, such as formal verification, linting, and mixed-signal simulations.
Regards, Victor Lyuboslavsky, creator of EDA Playground
Well, all I can say is that I am very impressed. Anything that makes learning this stuff and sharing things easier has to be a good thing. I would be very interested to hear your views on EDA Playground, especially if you've already been playing with it.