PORTLAND, Ore. -- The highest-performance metal-oxide-semiconductor field-effect-transistor (MOSFET) -- if not the fastest -- is no longer be made from silicon. It's made from III-V materials grown atop a silicon substrate, according to researchers at the 2014 VLSI Symposium in Honolulu, Hawaii.
In a demonstration supported by the Semiconductor Research Corporation, researchers from the University of California at Santa Barbara (UCSB) showed what they called the world's highest-performance MOSFET formed from indium-gallium-arsenide (InGaAs) atop indium-phosphide (InP), which can be grown on silicon (Si).
"The present substrate is InP. Other research groups, including IMEC, have shown that InP can be grown on Si," Mark Rodwell, professor of electrical and computer engineering at UCSB, told EE Times. "There is, indeed, at least one InGaAs-on-Si III-V MOS presentation at the VLSI Symposium. So, although our record devices are not on Si, it can certainly be done."
Transmission electron microscopy shows a 2.7-nanometer channel, sophisticated high-K dielectric, and other advanced features that researchers say make this the world's highest-performing MOSFET.
Not only did the III-V MOSFETs deliver higher performance than similar sized silicon transistors, but they also consumed less power. According to Rodwell, they will eventually overtake silicon FinFET transistors in speed and power consumption.
Even though the researchers have not measured switching speed yet, they estimate that, for RF/wireless applications, the III-V MOSFETs will run 30-60% faster than silicon RF. And since electron mobility is 2.5 to 3 times faster in InAs than Si, digital clock speeds are estimated to be significantly higher than Si.
For now, the "highest-performance" claim is based on the on-current (0.5 milliamps per micron width) and off-current (100 nano amps) of UCSB's III-V MOSFETs when produced in similar sizes and gate lengths (25 nm) and when operating at similar voltages (0.5 V) to Si. And Rodwell said future versions of the III-V MOSFET will significantly outperform silicon FinFETs of equal size.
Detailed layered architecture of the metal gate III-V MOSFET that researchers say outperforms silicon MOSFETs.
The tricks Rodwell's group used were based on fabricating the InAs semiconductor channels just 2.5 nm (17 atoms) thick. Doctoral candidate Cheng-Ying Huang accomplished that feat together with professor Arthur Gossard.
Doctoral candidate Varista Chobpattana, working with professor Susanne Stemmer, built sophisticated high-k gate dielectrics -- stacks of nickel-aluminum (NiAl) metal gates on layered stacks of alumina (Al2O3 on InAa) and zirconia (ZrO2) with very high capacitance density, thus enabling the high turned-on currents.
The final touches were applied in Rodwell's lab by doctoral candidate Sanghoon Lee, who designed the MOSFET adding a vertical spacer layer to cut current leakage by smoothly distributing the electric field so as to avoid band-to-band tunneling. The researchers say this produces off-currents that rival state-of-the-art silicon MOSFETs.
— R. Colin Johnson, Advanced Technology Editor, EE Times