Taylor had moved on to the University of Connecticut for several years before the Bell Labs patents expired on III-V chips. It was there that he resurrected the Bell Labs work, but transformed it from a single n-channel-only electrical/optical (EO) technology into a dual-channel electrical/optical technology aimed at extending Moore's Law indefinitely well into the future for complementary electrical/optical circuits. He renamed the technology Planar Opto Electronic Technology (POET). The University of Connecticut is now assigned the patents, with POET its exclusive licensee.
"Our planar electronic technology -- called PET -- is a major advance over previous GaAs technologies based on NMOS-like circuit structures, because we have integratable in-plane optical and electrical devices that are complementary -- so you can do CMOS," Daniel DeSimone, chief technical officer tells EE Times.
The channels of POET's transistors are InGaAs, which theoretically could reach 40,000 cm2/ (V·s) if the gallium was reduced to zero (pure bulk InAs). That however is not achievable, according to POET, although it is getting as close as it can. Thus far channels of 53% indium have been achieved and the company believes that 80% indium is ultimately possible.
POET's use of GaAs substrates allows it to include optical devices alongside electrical devices, allowing transistors and optical interconnects to co-exist on the same chip.
"We achieved these results by changing the lattice constant in a unique metamorphic way that fools nature," Taylor tells EE Times. "First we start with GaAs substrate, then we layer on top of that one micron strained layers of InGaAs over and over until we reach a layer that has natural quantum wells corresponding to the lattice constant of InP. It's all a question of the compositional control enabled by MBE [Molecular-beam epitaxy]."
POET has a deal with a third-party foundry to demonstrate a 100 nanometer process later this year and a 40 nanometer process by 2015. Those figures sound like they are behind silicon, which is already down to 20 nanometers and, at Intel, down to 14 nanometers. But POET argues that the comparison is not fair. Instead its 40 nanometer process should be compared to 14 and 10 nanometer in silicon.
"Our 40 nanometer GaAs compares to silicon 3 nodes ahead in speed and 4 nodes in power, with comparable integration density," DeSimone tells EE Times. "Thus 40 nanometer GaAs compares to 14 nanometer in speed and 10 nanometer in power."
— R. Colin Johnson, Advanced Technology Editor, EE Times